add multi-out pipe module (untested)

[ieee754fpu.git] / src / add / test_prioritymux_pipe.py

diff --git a/src/add/test_prioritymux_pipe.py b/src/add/test_prioritymux_pipe.py
index 7e71d7fd2c37a709259bf3466d2874ea4ed5084d..6b41f1b4d30535864db7e82b2e21e32634549f99 100644 (file)
--- a/src/add/test_prioritymux_pipe.py
+++ b/src/add/test_prioritymux_pipe.py
@@ -216,7 +216,7 @@ class InputTest:
 
 class TestPriorityMuxPipe(PriorityUnbufferedPipeline):
     def __init__(self):
-        self.num_rows = 2
+        self.num_rows = 4
         stage = PassThroughStage()
         PriorityUnbufferedPipeline.__init__(self, stage, p_len=self.num_rows)
 
@@ -239,7 +239,7 @@ if __name__ == '__main__':
 
     test = InputTest(dut)
     run_simulation(dut, [test.send(1), test.send(0),
-                         #test.send(3), test.send(2),
+                         test.send(3), test.send(2),
                          test.rcv()],
                    vcd_name="test_inputgroup_multi.vcd")