looking for replacements of the hard-coded control blocks

[ieee754fpu.git] / src / add / test_prioritymux_pipe.py

diff --git a/src/add/test_prioritymux_pipe.py b/src/add/test_prioritymux_pipe.py
index 7e71d7fd2c37a709259bf3466d2874ea4ed5084d..819f41f84bdf8b7b7a8edb3be34c707404148cf8 100644 (file)
--- a/src/add/test_prioritymux_pipe.py
+++ b/src/add/test_prioritymux_pipe.py
@@ -4,19 +4,10 @@ from nmigen import Module, Signal, Cat
 from nmigen.compat.sim import run_simulation
 from nmigen.cli import verilog, rtlil
 
-from multipipe import CombMultiInPipeline, InputPriorityArbiter
+from singlepipe import PassThroughStage
+from multipipe import (CombMultiInPipeline, PriorityCombMuxInPipe)
 
 
-
-class PriorityUnbufferedPipeline(CombMultiInPipeline):
-    def __init__(self, stage, p_len=4):
-        p_mux = InputPriorityArbiter(self, p_len)
-        CombMultiInPipeline.__init__(self, stage, p_len=p_len, p_mux=p_mux)
-
-    def ports(self):
-        return self.p_mux.ports()
-        #return UnbufferedPipeline.ports(self) + self.p_mux.ports()
-
 class PassData:
     def __init__(self):
         self.mid = Signal(2, reset_less=True)
@@ -29,16 +20,6 @@ class PassData:
     def ports(self):
         return [self.mid, self.idx, self.data]
 
-class PassThroughStage:
-    def ispec(self):
-        return PassData()
-    def ospec(self):
-        return self.ispec() # same as ospec
-                
-    def process(self, i):
-        return i # pass-through
-
-
 
 def testbench(dut):
     stb = yield dut.out_op.stb
@@ -214,20 +195,12 @@ class InputTest:
                 break
 
 
-class TestPriorityMuxPipe(PriorityUnbufferedPipeline):
+class TestPriorityMuxPipe(PriorityCombMuxInPipe):
     def __init__(self):
-        self.num_rows = 2
-        stage = PassThroughStage()
-        PriorityUnbufferedPipeline.__init__(self, stage, p_len=self.num_rows)
-
-    def ports(self):
-        res = []
-        for i in range(len(self.p)):
-            res += [self.p[i].i_valid, self.p[i].o_ready] + \
-                    self.p[i].i_data.ports()
-        res += [self.n.i_ready, self.n.o_valid] + \
-                self.n.o_data.ports()
-        return res
+        self.num_rows = 4
+        def iospecfn(): return PassData()
+        stage = PassThroughStage(iospecfn)
+        PriorityCombMuxInPipe.__init__(self, stage, p_len=self.num_rows)
 
 
 if __name__ == '__main__':
@@ -239,7 +212,7 @@ if __name__ == '__main__':
 
     test = InputTest(dut)
     run_simulation(dut, [test.send(1), test.send(0),
-                         #test.send(3), test.send(2),
+                         test.send(3), test.send(2),
                          test.rcv()],
                    vcd_name="test_inputgroup_multi.vcd")