add (but comment out) reset signal

[ieee754fpu.git] / src / add / unit_test_single.py

diff --git a/src/add/unit_test_single.py b/src/add/unit_test_single.py
index c5e66c4d1b0f644535f3d004bf6310eea60436e7..3c3c6291938659c72e6dae9cc6d6d05ca5572011 100644 (file)
--- a/src/add/unit_test_single.py
+++ b/src/add/unit_test_single.py
@@ -36,42 +36,52 @@ def match(x, y):
         (x == y)
         )
 
-def get_case(dut, a, b):
-    yield dut.in_a.v.eq(a)
-    yield dut.in_a.stb.eq(1)
+def get_case(dut, a, b, mid):
+    in_a, in_b = dut.rs[0]
+    out_z = dut.res[0]
+    yield dut.ids.in_mid.eq(mid)
+    yield in_a.v.eq(a)
+    yield in_a.stb.eq(1)
     yield
     yield
-    a_ack = (yield dut.in_a.ack)
+    yield
+    yield
+    a_ack = (yield in_a.ack)
     assert a_ack == 0
 
-    yield dut.in_a.stb.eq(0)
+    yield in_a.stb.eq(0)
 
-    yield dut.in_b.v.eq(b)
-    yield dut.in_b.stb.eq(1)
+    yield in_b.v.eq(b)
+    yield in_b.stb.eq(1)
     yield
     yield
-    b_ack = (yield dut.in_b.ack)
+    b_ack = (yield in_b.ack)
     assert b_ack == 0
 
-    yield dut.in_b.stb.eq(0)
+    yield in_b.stb.eq(0)
 
-    yield dut.out_z.ack.eq(1)
+    yield out_z.ack.eq(1)
 
     while True:
-        out_z_stb = (yield dut.out_z.stb)
+        out_z_stb = (yield out_z.stb)
         if not out_z_stb:
             yield
             continue
-        out_z = yield dut.out_z.v
-        yield dut.out_z.ack.eq(0)
+        vout_z = yield out_z.v
+        #out_mid = yield dut.ids.out_mid
+        yield out_z.ack.eq(0)
         yield
         break
 
-    return out_z
+    return vout_z, mid
 
-def check_case(dut, a, b, z):
-    out_z = yield from get_case(dut, a, b)
+def check_case(dut, a, b, z, mid=None):
+    if mid is None:
+        mid = randint(0, 6)
+    mid = 0
+    out_z, out_mid = yield from get_case(dut, a, b, mid)
     assert out_z == z, "Output z 0x%x not equal to expected 0x%x" % (out_z, z)
+    assert out_mid == mid, "Output mid 0x%x != expected 0x%x" % (out_mid, mid)
 
 
 def run_test(dut, stimulus_a, stimulus_b, op):
@@ -79,12 +89,14 @@ def run_test(dut, stimulus_a, stimulus_b, op):
     expected_responses = []
     actual_responses = []
     for a, b in zip(stimulus_a, stimulus_b):
+        mid = randint(0, 6)
+        mid = 0
         af = Float32.from_bits(a)
         bf = Float32.from_bits(b)
         z = op(af, bf)
-        expected_responses.append(z.get_bits())
+        expected_responses.append((z.get_bits(), mid))
         #print (af, bf, z)
-        actual = yield from get_case(dut, a, b)
+        actual = yield from get_case(dut, a, b, mid)
         actual_responses.append(actual)
 
     if len(actual_responses) < len(expected_responses):
@@ -93,7 +105,10 @@ def run_test(dut, stimulus_a, stimulus_b, op):
 
     for expected, actual, a, b in zip(expected_responses, actual_responses,
                                       stimulus_a, stimulus_b):
-        passed = match(expected, actual)
+        passed = match(expected[0], actual[0])
+        if expected[1] != actual[1]: # check mid
+            print ("MID failed", expected[1], actual[1])
+            sys.exit(0)
 
         if not passed:
 
@@ -186,7 +201,7 @@ def run_edge_cases(dut, count, op):
         count = yield from run_cases(dut, count, op, testme, 10)
 
     for i in range(100000):
-        stimulus_a = [randint(0, 1<<32) for i in range(1000)]
-        count = yield from run_cases(dut, count, op, stimulus_a, 1000)
+        stimulus_a = [randint(0, 1<<32) for i in range(10)]
+        count = yield from run_cases(dut, count, op, stimulus_a, 10)
     return count