from power_decoder import (PowerDecoder)
from power_enums import (Function, InternalOp, In1Sel, In2Sel, In3Sel,
OutSel, RC, LdstLen, CryIn, single_bit_flags,
- get_signal_name)
+ get_signal_name, get_csv)
class DecoderTestCase(FHDLTestCase):
- def run_test(self, width, csvname, opint=True):
+ def run_test(self, width, csvname, suffix=None, opint=True):
m = Module()
comb = m.d.comb
opcode = Signal(width)
ldst_len = Signal(LdstLen)
cry_in = Signal(CryIn)
- m.submodules.dut = dut = PowerDecoder(width, csvname, opint)
+ opcodes = get_csv(csvname)
+ m.submodules.dut = dut = PowerDecoder(width, opcodes, opint, suffix=suffix)
comb += [dut.opcode_in.eq(opcode),
function_unit.eq(dut.op.function_unit),
in1_sel.eq(dut.op.in1_sel),
in1_sel, in2_sel]):
sim.run()
- def generate_ilang(self, width, csvname, opint=True):
+ def generate_ilang(self, width, csvname, opint=True, suffix=None):
prefix = os.path.splitext(csvname)[0]
- dut = PowerDecoder(width, csvname, opint)
+ dut = PowerDecoder(width, get_csv(csvname), opint, suffix=suffix)
vl = rtlil.convert(dut, ports=dut.ports())
with open("%s_decoder.il" % prefix, "w") as f:
f.write(vl)
self.run_test(6, "major.csv")
self.generate_ilang(6, "major.csv")
- def test_minor_19(self):
- self.run_test(3, "minor_19.csv")
- self.generate_ilang(3, "minor_19.csv")
+ # def test_minor_19(self):
+ # self.run_test(3, "minor_19.csv")
+ # self.generate_ilang(3, "minor_19.csv")
def test_minor_30(self):
self.run_test(4, "minor_30.csv")
self.generate_ilang(4, "minor_30.csv")
def test_minor_31(self):
- self.run_test(10, "minor_31.csv")
- self.generate_ilang(10, "minor_31.csv")
+ self.run_test(10, "minor_31.csv", suffix=(0, 5))
+ self.generate_ilang(10, "minor_31.csv", suffix=(0, 5))
- def test_minor_31(self):
+ def test_extra(self):
self.run_test(32, "extra.csv", False)
self.generate_ilang(32, "extra.csv", False)