Minor cleanup

[soc.git] / src / decoder / test / test_power_major_decoder.py

diff --git a/src/decoder/test/test_power_major_decoder.py b/src/decoder/test/test_power_major_decoder.py
index 05d9b13c7eef175ac2df11523fbd837e871a78b4..321772eb445320cec39ce1b091085093f3dea877 100644 (file)
--- a/src/decoder/test/test_power_major_decoder.py
+++ b/src/decoder/test/test_power_major_decoder.py
@@ -1,12 +1,13 @@
-from nmigen import Module, Elaboratable, Signal
-from nmigen.back.pysim import Simulator, Delay, Settle
+from nmigen import Module, Signal
+from nmigen.back.pysim import Simulator, Delay
 from nmigen.test.utils import FHDLTestCase
 from nmigen.cli import rtlil
 import sys
 import unittest
 sys.path.append("../")
 from power_major_decoder import (PowerMajorDecoder, Function,
-                                InternalOp, major_opcodes)
+                                 InternalOp, major_opcodes)
+
 
 class DecoderTestCase(FHDLTestCase):
     def test_function_unit(self):
@@ -22,6 +23,7 @@ class DecoderTestCase(FHDLTestCase):
                  internal_op.eq(dut.internal_op)]
 
         sim = Simulator(m)
+
         def process():
             for row in major_opcodes:
                 yield opcode.eq(int(row['opcode']))
@@ -34,15 +36,16 @@ class DecoderTestCase(FHDLTestCase):
                 expected = InternalOp[row['internal op']].value
                 self.assertEqual(expected, result)
         sim.add_process(process)
-        with sim.write_vcd("test.vcd", "test.gtkw", traces=[opcode, function_unit, internal_op]):
+        with sim.write_vcd("test.vcd", "test.gtkw", traces=[
+                opcode, function_unit, internal_op]):
             sim.run()
 
     def test_ilang(self):
         dut = PowerMajorDecoder()
-        vl = rtlil.convert(dut, ports=[dut.opcode_in, dut.function_unit])
+        vl = rtlil.convert(dut, ports=dut.ports())
         with open("power_major_decoder.il", "w") as f:
             f.write(vl)
 
+
 if __name__ == "__main__":
     unittest.main()
-