sync ok on simple add

[soc.git] / src / experiment / compalu.py

diff --git a/src/experiment/compalu.py b/src/experiment/compalu.py
index 016b910418a9dc9033ff21f4421fc3d068dc67a7..71a4c68008a1aee98f580cf30bf6b9ba030cd2ee 100644 (file)
--- a/src/experiment/compalu.py
+++ b/src/experiment/compalu.py
@@ -36,16 +36,16 @@ class ComputationUnitNoDelay(Elaboratable):
         # latches be set at the same time.
 
         # opcode latch (not using go_rd_i) - inverted so that busy resets to 0
-        m.d.comb += opc_l.s.eq(self.issue_i) # XXX NOTE: INVERTED FROM book!
-        m.d.comb += opc_l.r.eq(self.go_wr_i) # XXX NOTE: INVERTED FROM book!
+        m.d.sync += opc_l.s.eq(self.issue_i) # XXX NOTE: INVERTED FROM book!
+        m.d.sync += opc_l.r.eq(self.go_wr_i) # XXX NOTE: INVERTED FROM book!
 
         # src operand latch (not using go_wr_i)
-        m.d.comb += src_l.s.eq(self.issue_i)
-        m.d.comb += src_l.r.eq(self.go_rd_i)
+        m.d.sync += src_l.s.eq(self.issue_i)
+        m.d.sync += src_l.r.eq(self.go_rd_i)
 
         # dest operand latch (not using issue_i)
-        m.d.comb += req_l.s.eq(self.go_rd_i)
-        m.d.comb += req_l.r.eq(self.go_wr_i)
+        m.d.sync += req_l.s.eq(self.go_rd_i)
+        m.d.sync += req_l.r.eq(self.go_wr_i)
 
         # XXX
         # XXX NOTE: sync on req_rel_o and data_o due to simulation lock-up