getting there with instruction overlapping

[soc.git] / src / experiment / compalu.py

diff --git a/src/experiment/compalu.py b/src/experiment/compalu.py
index 3c97c19af99c9938c86a056477492864244ca948..cd781603c243f5f71eaec0ec52cd5aded1842b23 100644 (file)
--- a/src/experiment/compalu.py
+++ b/src/experiment/compalu.py
@@ -53,11 +53,11 @@ class ComputationUnitNoDelay(Elaboratable):
         # outputs
         m.d.comb += self.busy_o.eq(opc_l.q) # busy out
 
-        with m.If(self.go_rd_i):
-            m.d.sync += self.counter.eq(2)
+        with m.If(src_l.q & (self.counter == 0)):
+            m.d.sync += self.counter.eq(3)
         with m.If(self.counter > 0):
             m.d.sync += self.counter.eq(self.counter - 1)
-        with m.If(self.counter == 1):
+        with m.If((self.counter == 1) | (self.counter == 0)):
             m.d.comb += self.req_rel_o.eq(req_l.q & opc_l.q) # req release out
 
         # create a latch/register for src1/src2