use register latching in Computation Unit

[soc.git] / src / experiment / score6600.py

diff --git a/src/experiment/score6600.py b/src/experiment/score6600.py
index c2ec3d89732be9f906daf8cebe1b1d130d8ee24b..12d9e0799337b6b331813be65c5b169ff479e396 100644 (file)
--- a/src/experiment/score6600.py
+++ b/src/experiment/score6600.py
@@ -306,11 +306,12 @@ def scoreboard_sim(dut, alusim):
             break
             if dest not in [src1, src2]:
                 break
-        #src1 = 7
-        #src2 = 7
+        src1 = 1
+        src2 = 7
         dest = src2
 
         op = randint(0, 1)
+        op = 0
         print ("random %d: %d %d %d %d\n" % (i, op, src1, src2, dest))
         yield from int_instr(dut, alusim, op, src1, src2, dest)
         yield from print_reg(dut, [3,4,5])