move test_buf_pipe.py unit test, shuffle nmutil

[ieee754fpu.git] / src / ieee754 / add / test_prioritymux_pipe.py

diff --git a/src/ieee754/add/test_prioritymux_pipe.py b/src/ieee754/add/test_prioritymux_pipe.py
index 5f7891e881271fad4ba5f730d8d9070c29e38024..ca7181d0df4d99567873998d09dc444cb57f740c 100644 (file)
--- a/src/ieee754/add/test_prioritymux_pipe.py
+++ b/src/ieee754/add/test_prioritymux_pipe.py
@@ -4,8 +4,8 @@ from nmigen import Module, Signal, Cat
 from nmigen.compat.sim import run_simulation
 from nmigen.cli import verilog, rtlil
 
-from singlepipe import PassThroughStage
-from multipipe import (CombMultiInPipeline, PriorityCombMuxInPipe)
+from nmutil.singlepipe import PassThroughStage
+from nmutil.multipipe import (CombMultiInPipeline, PriorityCombMuxInPipe)
 
 
 class PassData: