Add cordic stages to fp cordic pipeline

[ieee754fpu.git] / src / ieee754 / cordic / test / test_fp_pipe.py

diff --git a/src/ieee754/cordic/test/test_fp_pipe.py b/src/ieee754/cordic/test/test_fp_pipe.py
index 1b2ead125381d366065fd0c943f85e9c3dd51c96..295c3c4f3c42c3596a441750c6eefc467a652768 100644 (file)
--- a/src/ieee754/cordic/test/test_fp_pipe.py
+++ b/src/ieee754/cordic/test/test_fp_pipe.py
@@ -47,7 +47,7 @@ class SinCosTestCase(FHDLTestCase):
 
         sim.add_sync_process(writer_process)
         with sim.write_vcd("fp_pipeline.vcd", "fp_pipeline.gtkw", traces=[
-                z, dut.n.data_o.z0]):
+                z]):
             sim.run()
 
     def test_rand(self):