Cleanup

[ieee754fpu.git] / src / ieee754 / cordic / test / test_pipe.py

diff --git a/src/ieee754/cordic/test/test_pipe.py b/src/ieee754/cordic/test/test_pipe.py
index bcfd563f0d936d3abaabf883474cb55a51b055e7..809ca7f7f5ae0f249c4e4679a681d9e4cb1d9a12 100644 (file)
--- a/src/ieee754/cordic/test/test_pipe.py
+++ b/src/ieee754/cordic/test/test_pipe.py
@@ -1,5 +1,5 @@
 from nmigen import Module, Signal
-from nmigen.back.pysim import Simulator, Delay, Passive
+from nmigen.back.pysim import Simulator, Passive
 from nmigen.test.utils import FHDLTestCase
 
 from ieee754.cordic.sin_cos_pipeline import CordicBasePipe
@@ -57,14 +57,12 @@ class SinCosTestCase(FHDLTestCase):
                     except StopIteration:
                         break
 
-
         sim.add_sync_process(writer_process)
         sim.add_sync_process(reader_process)
         with sim.write_vcd("pipeline.vcd", "pipeline.gtkw", traces=[
                 z, x, y]):
             sim.run()
 
-
     def test_rand(self):
         fracbits = 16
         M = (1 << fracbits)
@@ -79,6 +77,5 @@ class SinCosTestCase(FHDLTestCase):
         self.run_test(iter(inputs), iter(outputs), fracbits=fracbits)
 
 
-
 if __name__ == "__main__":
     unittest.main()