Combine a selectable number of rounds into one pipeline stage

[ieee754fpu.git] / src / ieee754 / cordic / test / test_pipe.py

diff --git a/src/ieee754/cordic/test/test_pipe.py b/src/ieee754/cordic/test/test_pipe.py
index 809ca7f7f5ae0f249c4e4679a681d9e4cb1d9a12..880351ade028b4d89190685beb40298e261fc9f1 100644 (file)
--- a/src/ieee754/cordic/test/test_pipe.py
+++ b/src/ieee754/cordic/test/test_pipe.py
@@ -13,7 +13,7 @@ import random
 class SinCosTestCase(FHDLTestCase):
     def run_test(self, inputs, outputs, fracbits=8):
         m = Module()
-        pspec = CordicPipeSpec(fracbits=fracbits)
+        pspec = CordicPipeSpec(fracbits=fracbits, rounds_per_stage=4)
         m.submodules.dut = dut = CordicBasePipe(pspec)
 
         z = Signal(dut.p.data_i.z0.shape())