Revert "reduce LHS for RSQRT by a factor of fract_width and"

[ieee754fpu.git] / src / ieee754 / div_rem_sqrt_rsqrt / core.py

diff --git a/src/ieee754/div_rem_sqrt_rsqrt/core.py b/src/ieee754/div_rem_sqrt_rsqrt/core.py
index 1c1e4c296b12ac2c0ac6a4b12b96bb09cd9f6b8e..b62a9574d2684320590859ca126c680e69fcb696 100644 (file)
--- a/src/ieee754/div_rem_sqrt_rsqrt/core.py
+++ b/src/ieee754/div_rem_sqrt_rsqrt/core.py
@@ -78,6 +78,7 @@ class DivPipeCoreOperation(enum.Enum):
 
 DP = DivPipeCoreOperation
 
+
 class DivPipeCoreInputData:
     """ input data type for ``DivPipeCore``.
 
@@ -249,7 +250,7 @@ class DivPipeCoreSetupStage(Elaboratable):
                 self.i.divisor_radicand << (self.core_config.fract_width * 2))
         with m.Else():  # DivPipeCoreOperation.RSqrtRem
             m.d.comb += self.o.compare_lhs.eq(
-                1 << (self.core_config.fract_width * 2)) # XXX reduced from 3
+                1 << (self.core_config.fract_width * 3))
 
         m.d.comb += self.o.compare_rhs.eq(0)
         m.d.comb += self.o.operation.eq(self.i.operation)