split out div/sqrt/rsqrt trials to separate module

[ieee754fpu.git] / src / ieee754 / div_rem_sqrt_rsqrt / test_core.py

diff --git a/src/ieee754/div_rem_sqrt_rsqrt/test_core.py b/src/ieee754/div_rem_sqrt_rsqrt/test_core.py
index fc42829ba24a3cbe51b0ce4b5e3a3a3a2fd03356..95292f9afbf95e6198dc05e7a1864bcd420f8d54 100755 (executable)
--- a/src/ieee754/div_rem_sqrt_rsqrt/test_core.py
+++ b/src/ieee754/div_rem_sqrt_rsqrt/test_core.py
@@ -257,8 +257,10 @@ class TestDivPipeCore(unittest.TestCase):
                     remainder = (yield dut.o.remainder)
                     with self.subTest(test_case=str(test_case)):
                         self.assertEqual(quotient_root,
-                                         test_case.quotient_root)
-                        self.assertEqual(remainder, test_case.remainder)
+                                         test_case.quotient_root,
+                                         str(test_case))
+                        self.assertEqual(remainder, test_case.remainder,
+                                         str(test_case))
             sim.add_clock(2e-6)
             sim.add_sync_process(generate_process)
             sim.add_sync_process(check_process)