use Mux instead of m.If/Elif on add sign

[ieee754fpu.git] / src / ieee754 / fpadd / add0.py

diff --git a/src/ieee754/fpadd/add0.py b/src/ieee754/fpadd/add0.py
index 2110f81bfafd26d773cc9c09948e01766fa5e2d1..c3300a60410d659a9307638312cfbe175f69222e 100644 (file)
--- a/src/ieee754/fpadd/add0.py
+++ b/src/ieee754/fpadd/add0.py
@@ -4,7 +4,7 @@ Copyright (C) 2019 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 
 """
 
-from nmigen import Module, Signal, Cat
+from nmigen import Module, Signal, Cat, Mux
 from nmigen.cli import main, verilog
 
 from nmutil.pipemodbase import PipeModBase
@@ -35,30 +35,27 @@ class FPAddStage0Mod(PipeModBase):
         am0 = Signal(len(self.i.a.m)+1, reset_less=True)
         bm0 = Signal(len(self.i.b.m)+1, reset_less=True)
         # same-sign (both negative or both positive) add mantissas
-        with m.If(~self.i.out_do_z):
-            comb += [seq.eq(self.i.a.s == self.i.b.s),
-                     mge.eq(self.i.a.m >= self.i.b.m),
-                     am0.eq(Cat(self.i.a.m, 0)),
-                     bm0.eq(Cat(self.i.b.m, 0))
-                    ]
-            comb += self.o.z.e.eq(self.i.a.e)
-            with m.If(seq):
-                comb += [
-                    self.o.tot.eq(am0 + bm0),
-                    self.o.z.s.eq(self.i.a.s)
+        comb += [seq.eq(self.i.a.s == self.i.b.s),
+                 mge.eq(self.i.a.m >= self.i.b.m),
+                 am0.eq(Cat(self.i.a.m, 0)),
+                 bm0.eq(Cat(self.i.b.m, 0))
                 ]
-            # a mantissa greater than b, use a
-            with m.Elif(mge):
-                comb += [
-                    self.o.tot.eq(am0 - bm0),
-                    self.o.z.s.eq(self.i.a.s)
-                ]
-            # b mantissa greater than a, use b
-            with m.Else():
-                comb += [
-                    self.o.tot.eq(bm0 - am0),
-                    self.o.z.s.eq(self.i.b.s)
+        comb += self.o.z.e.eq(self.i.a.e)
+        comb += self.o.z.s.eq(Mux(seq | mge, self.i.a.s, self.i.b.s))
+        with m.If(seq):
+            comb += [
+                self.o.tot.eq(am0 + bm0),
+            ]
+        # a mantissa greater than b, use a
+        with m.Elif(mge):
+            comb += [
+                self.o.tot.eq(am0 - bm0),
             ]
+        # b mantissa greater than a, use b
+        with m.Else():
+            comb += [
+                self.o.tot.eq(bm0 - am0),
+        ]
 
         # pass-through context
         comb += self.o.oz.eq(self.i.oz)