use Mux instead of m.If/Elif on add sign

[ieee754fpu.git] / src / ieee754 / fpadd / add0.py

diff --git a/src/ieee754/fpadd/add0.py b/src/ieee754/fpadd/add0.py
index fd90887932704ac0623a77411bb320bb29a439de..c3300a60410d659a9307638312cfbe175f69222e 100644 (file)
--- a/src/ieee754/fpadd/add0.py
+++ b/src/ieee754/fpadd/add0.py
@@ -4,30 +4,14 @@ Copyright (C) 2019 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 
 """
 
-from nmigen import Module, Signal, Cat
+from nmigen import Module, Signal, Cat, Mux
 from nmigen.cli import main, verilog
 
 from nmutil.pipemodbase import PipeModBase
 
-from ieee754.fpcommon.fpbase import FPNumBase, FPNumBaseRecord
 from ieee754.fpcommon.denorm import FPSCData
 from ieee754.fpcommon.getop import FPPipeContext
-
-
-class FPAddStage0Data:
-
-    def __init__(self, pspec):
-        width = pspec.width
-        self.z = FPNumBaseRecord(width, False)
-        self.out_do_z = Signal(reset_less=True)
-        self.oz = Signal(width, reset_less=True)
-        self.tot = Signal(self.z.m_width + 4, reset_less=True) # 4 extra bits
-        self.ctx = FPPipeContext(pspec)
-        self.muxid = self.ctx.muxid
-
-    def eq(self, i):
-        return [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz),
-                self.tot.eq(i.tot), self.ctx.eq(i.ctx)]
+from ieee754.fpadd.datastruct import FPAddStage0Data
 
 
 class FPAddStage0Mod(PipeModBase):
@@ -50,32 +34,28 @@ class FPAddStage0Mod(PipeModBase):
         mge = Signal(reset_less=True)
         am0 = Signal(len(self.i.a.m)+1, reset_less=True)
         bm0 = Signal(len(self.i.b.m)+1, reset_less=True)
-        comb += [seq.eq(self.i.a.s == self.i.b.s),
-                     mge.eq(self.i.a.m >= self.i.b.m),
-                     am0.eq(Cat(self.i.a.m, 0)),
-                     bm0.eq(Cat(self.i.b.m, 0))
-                    ]
-
         # same-sign (both negative or both positive) add mantissas
-        with m.If(~self.i.out_do_z):
-            comb += self.o.z.e.eq(self.i.a.e)
-            with m.If(seq):
-                comb += [
-                    self.o.tot.eq(am0 + bm0),
-                    self.o.z.s.eq(self.i.a.s)
-                ]
-            # a mantissa greater than b, use a
-            with m.Elif(mge):
-                comb += [
-                    self.o.tot.eq(am0 - bm0),
-                    self.o.z.s.eq(self.i.a.s)
+        comb += [seq.eq(self.i.a.s == self.i.b.s),
+                 mge.eq(self.i.a.m >= self.i.b.m),
+                 am0.eq(Cat(self.i.a.m, 0)),
+                 bm0.eq(Cat(self.i.b.m, 0))
                 ]
-            # b mantissa greater than a, use b
-            with m.Else():
-                comb += [
-                    self.o.tot.eq(bm0 - am0),
-                    self.o.z.s.eq(self.i.b.s)
+        comb += self.o.z.e.eq(self.i.a.e)
+        comb += self.o.z.s.eq(Mux(seq | mge, self.i.a.s, self.i.b.s))
+        with m.If(seq):
+            comb += [
+                self.o.tot.eq(am0 + bm0),
+            ]
+        # a mantissa greater than b, use a
+        with m.Elif(mge):
+            comb += [
+                self.o.tot.eq(am0 - bm0),
             ]
+        # b mantissa greater than a, use b
+        with m.Else():
+            comb += [
+                self.o.tot.eq(bm0 - am0),
+        ]
 
         # pass-through context
         comb += self.o.oz.eq(self.i.oz)