rename FPModBase* to PipeModBase*

[ieee754fpu.git] / src / ieee754 / fpadd / add0.py

diff --git a/src/ieee754/fpadd/add0.py b/src/ieee754/fpadd/add0.py
index 0a77855b9a1c4be9d616a6c9432f80ec942b5840..fd90887932704ac0623a77411bb320bb29a439de 100644 (file)
--- a/src/ieee754/fpadd/add0.py
+++ b/src/ieee754/fpadd/add0.py
@@ -7,7 +7,7 @@ Copyright (C) 2019 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 from nmigen import Module, Signal, Cat
 from nmigen.cli import main, verilog
 
-from nmutil.pipemodbase import FPModBase
+from nmutil.pipemodbase import PipeModBase
 
 from ieee754.fpcommon.fpbase import FPNumBase, FPNumBaseRecord
 from ieee754.fpcommon.denorm import FPSCData
@@ -30,7 +30,7 @@ class FPAddStage0Data:
                 self.tot.eq(i.tot), self.ctx.eq(i.ctx)]
 
 
-class FPAddStage0Mod(FPModBase):
+class FPAddStage0Mod(PipeModBase):
 
     def __init__(self, pspec):
         super().__init__(pspec, "add0")