add comments on parameters

[ieee754fpu.git] / src / ieee754 / fpcommon / denorm.py

diff --git a/src/ieee754/fpcommon/denorm.py b/src/ieee754/fpcommon/denorm.py
index cf54b0f3f0bf121d5fb4628fe03e285e1230a0e0..559c5ae244cc74191e3e7676dad6463e397ba7b0 100644 (file)
--- a/src/ieee754/fpcommon/denorm.py
+++ b/src/ieee754/fpcommon/denorm.py
@@ -2,23 +2,28 @@
 # Copyright (C) Jonathan P Dawson 2013
 # 2013-12-12
 
-from nmigen import Module, Signal
+from nmigen import Module, Signal, Elaboratable
 from nmigen.cli import main, verilog
 from math import log
 
-from ieee754.fpcommon.fpbase import FPNumIn, FPNumOut, FPNumBase
-from ieee754.fpcommon.fpbase import FPState
+from ieee754.fpcommon.fpbase import FPNumIn, FPNumOut, FPNumBaseRecord
+from ieee754.fpcommon.fpbase import FPState, FPNumBase
 
 
 class FPSCData:
 
-    def __init__(self, width, id_wid):
-        self.a = FPNumBase(width, True)
-        self.b = FPNumBase(width, True)
-        self.z = FPNumOut(width, False)
-        self.oz = Signal(width, reset_less=True)
-        self.out_do_z = Signal(reset_less=True)
-        self.mid = Signal(id_wid, reset_less=True)
+    def __init__(self, width, id_wid, m_extra=True):
+
+        # NOTE: difference between z and oz is that oz is created by
+        # special-cases module(s) and will propagate, along with its
+        # "bypass" signal out_do_z, through the pipeline, *disabling*
+        # all processing of all subsequent stages.
+        self.a = FPNumBaseRecord(width, m_extra)   # operand a
+        self.b = FPNumBaseRecord(width, m_extra)   # operand b
+        self.z = FPNumBaseRecord(width, False)     # denormed result 
+        self.oz = Signal(width, reset_less=True)   # "finished" (bypass) result
+        self.out_do_z = Signal(reset_less=True)    # "bypass" enabled
+        self.mid = Signal(id_wid, reset_less=True) # multiplexer ID
 
     def __iter__(self):
         yield from self.a
@@ -33,19 +38,20 @@ class FPSCData:
                 self.a.eq(i.a), self.b.eq(i.b), self.mid.eq(i.mid)]
 
 
-class FPAddDeNormMod(FPState):
+class FPAddDeNormMod(FPState, Elaboratable):
 
-    def __init__(self, width, id_wid):
+    def __init__(self, width, id_wid, m_extra=True):
         self.width = width
         self.id_wid = id_wid
+        self.m_extra = m_extra
         self.i = self.ispec()
         self.o = self.ospec()
 
     def ispec(self):
-        return FPSCData(self.width, self.id_wid)
+        return FPSCData(self.width, self.id_wid, self.m_extra)
 
     def ospec(self):
-        return FPSCData(self.width, self.id_wid)
+        return FPSCData(self.width, self.id_wid, self.m_extra)
 
     def process(self, i):
         return self.o
@@ -58,21 +64,22 @@ class FPAddDeNormMod(FPState):
 
     def elaborate(self, platform):
         m = Module()
-        m.submodules.denorm_in_a = self.i.a
-        m.submodules.denorm_in_b = self.i.b
-        m.submodules.denorm_out_a = self.o.a
-        m.submodules.denorm_out_b = self.o.b
+        m.submodules.denorm_in_a = in_a = FPNumBase(self.i.a)
+        m.submodules.denorm_in_b = in_b = FPNumBase(self.i.b)
+        #m.submodules.denorm_out_a = self.o.a
+        #m.submodules.denorm_out_b = self.o.b
+        #m.submodules.denorm_out_z = self.o.z
 
         with m.If(~self.i.out_do_z):
             # XXX hmmm, don't like repeating identical code
             m.d.comb += self.o.a.eq(self.i.a)
-            with m.If(self.i.a.exp_n127):
+            with m.If(in_a.exp_n127):
                 m.d.comb += self.o.a.e.eq(self.i.a.N126) # limit a exponent
             with m.Else():
                 m.d.comb += self.o.a.m[-1].eq(1) # set top mantissa bit
 
             m.d.comb += self.o.b.eq(self.i.b)
-            with m.If(self.i.b.exp_n127):
+            with m.If(in_b.exp_n127):
                 m.d.comb += self.o.b.e.eq(self.i.b.N126) # limit a exponent
             with m.Else():
                 m.d.comb += self.o.b.m[-1].eq(1) # set top mantissa bit
@@ -90,8 +97,8 @@ class FPAddDeNorm(FPState):
     def __init__(self, width, id_wid):
         FPState.__init__(self, "denormalise")
         self.mod = FPAddDeNormMod(width)
-        self.out_a = FPNumBase(width)
-        self.out_b = FPNumBase(width)
+        self.out_a = FPNumBaseRecord(width)
+        self.out_b = FPNumBaseRecord(width)
 
     def setup(self, m, i):
         """ links module to inputs and outputs