big convert g/s/r mid --> muxid

[ieee754fpu.git] / src / ieee754 / fpcommon / denorm.py

diff --git a/src/ieee754/fpcommon/denorm.py b/src/ieee754/fpcommon/denorm.py
index fe1cc9de761edbe9ef86347e6c8fe270bea675f3..5c20e5359ef1ce41f1b806be27a15eeba068458c 100644 (file)
--- a/src/ieee754/fpcommon/denorm.py
+++ b/src/ieee754/fpcommon/denorm.py
@@ -8,17 +8,24 @@ from math import log
 
 from ieee754.fpcommon.fpbase import FPNumIn, FPNumOut, FPNumBaseRecord
 from ieee754.fpcommon.fpbase import FPState, FPNumBase
+from ieee754.fpcommon.getop import FPBaseData
 
 
 class FPSCData:
 
-    def __init__(self, width, id_wid, m_extra=True):
-        self.a = FPNumBase(width, m_extra)
-        self.b = FPNumBase(width, m_extra)
-        self.z = FPNumOut(width, False)
-        self.oz = Signal(width, reset_less=True)
-        self.out_do_z = Signal(reset_less=True)
-        self.mid = Signal(id_wid, reset_less=True)
+    def __init__(self, width, pspec, m_extra):
+
+        # NOTE: difference between z and oz is that oz is created by
+        # special-cases module(s) and will propagate, along with its
+        # "bypass" signal out_do_z, through the pipeline, *disabling*
+        # all processing of all subsequent stages.
+        self.a = FPNumBaseRecord(width, m_extra)   # operand a
+        self.b = FPNumBaseRecord(width, m_extra)   # operand b
+        self.z = FPNumBaseRecord(width, False)     # denormed result 
+        self.oz = Signal(width, reset_less=True)   # "finished" (bypass) result
+        self.out_do_z = Signal(reset_less=True)    # "bypass" enabled
+        self.ctx = FPBaseData(width, pspec) 
+        self.muxid = self.ctx.muxid
 
     def __iter__(self):
         yield from self.a
@@ -26,27 +33,28 @@ class FPSCData:
         yield from self.z
         yield self.oz
         yield self.out_do_z
-        yield self.mid
+        yield from self.ctx
 
     def eq(self, i):
-        return [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz),
-                self.a.eq(i.a), self.b.eq(i.b), self.mid.eq(i.mid)]
+        ret = [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz),
+                self.a.eq(i.a), self.b.eq(i.b), self.ctx.eq(i.ctx)]
+        return ret
 
 
 class FPAddDeNormMod(FPState, Elaboratable):
 
-    def __init__(self, width, id_wid, m_extra=True):
+    def __init__(self, width, pspec, m_extra):
         self.width = width
-        self.id_wid = id_wid
+        self.pspec = pspec
         self.m_extra = m_extra
         self.i = self.ispec()
         self.o = self.ospec()
 
     def ispec(self):
-        return FPSCData(self.width, self.id_wid, self.m_extra)
+        return FPSCData(self.width, self.pspec, self.m_extra)
 
     def ospec(self):
-        return FPSCData(self.width, self.id_wid, self.m_extra)
+        return FPSCData(self.width, self.pspec, self.m_extra)
 
     def process(self, i):
         return self.o
@@ -59,28 +67,27 @@ class FPAddDeNormMod(FPState, Elaboratable):
 
     def elaborate(self, platform):
         m = Module()
-        m.submodules.denorm_in_a = self.i.a
-        m.submodules.denorm_in_b = self.i.b
-        m.submodules.denorm_in_z = self.i.z
-        m.submodules.denorm_out_a = self.o.a
-        m.submodules.denorm_out_b = self.o.b
-        m.submodules.denorm_out_z = self.o.z
+        m.submodules.denorm_in_a = in_a = FPNumBase(self.i.a)
+        m.submodules.denorm_in_b = in_b = FPNumBase(self.i.b)
+        #m.submodules.denorm_out_a = self.o.a
+        #m.submodules.denorm_out_b = self.o.b
+        #m.submodules.denorm_out_z = self.o.z
 
         with m.If(~self.i.out_do_z):
             # XXX hmmm, don't like repeating identical code
             m.d.comb += self.o.a.eq(self.i.a)
-            with m.If(self.i.a.exp_n127):
+            with m.If(in_a.exp_n127):
                 m.d.comb += self.o.a.e.eq(self.i.a.N126) # limit a exponent
             with m.Else():
                 m.d.comb += self.o.a.m[-1].eq(1) # set top mantissa bit
 
             m.d.comb += self.o.b.eq(self.i.b)
-            with m.If(self.i.b.exp_n127):
+            with m.If(in_b.exp_n127):
                 m.d.comb += self.o.b.e.eq(self.i.b.N126) # limit a exponent
             with m.Else():
                 m.d.comb += self.o.b.m[-1].eq(1) # set top mantissa bit
 
-        m.d.comb += self.o.mid.eq(self.i.mid)
+        m.d.comb += self.o.ctx.eq(self.i.ctx)
         m.d.comb += self.o.z.eq(self.i.z)
         m.d.comb += self.o.out_do_z.eq(self.i.out_do_z)
         m.d.comb += self.o.oz.eq(self.i.oz)
@@ -93,8 +100,8 @@ class FPAddDeNorm(FPState):
     def __init__(self, width, id_wid):
         FPState.__init__(self, "denormalise")
         self.mod = FPAddDeNormMod(width)
-        self.out_a = FPNumBase(width)
-        self.out_b = FPNumBase(width)
+        self.out_a = FPNumBaseRecord(width)
+        self.out_b = FPNumBaseRecord(width)
 
     def setup(self, m, i):
         """ links module to inputs and outputs