-# IEEE Floating Point Adder (Single Precision)
-# Copyright (C) Jonathan P Dawson 2013
-# 2013-12-12
+"""IEEE754 Floating Point Library
-from nmigen import Signal, Cat, Const, Mux, Module, Elaboratable
+Copyright (C) 2019 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Copyright (C) 2019,2022 Jacob Lifshay <programmerjake@gmail.com>
+
+"""
+
+
+from nmigen import (Signal, Cat, Const, Mux, Module, Elaboratable, Array,
+ Value, Shape)
from math import log
from operator import or_
from functools import reduce
from nmutil.pipeline import ObjectProxy
import unittest
import math
+import enum
+
+try:
+ from nmigen.hdl.smtlib2 import RoundingModeEnum
+ _HAVE_SMTLIB2 = True
+except ImportError:
+ _HAVE_SMTLIB2 = False
+
+# value so FPRoundingMode.to_smtlib2 can detect when no default is supplied
+_raise_err = object()
+
+
+class FPRoundingMode(enum.Enum):
+ # matches the FPSCR.RN field values, but includes some extra
+ # values (>= 0b100) used in miscellaneous instructions.
+
+ # naming matches smtlib2 names, doc strings are the OpenPower ISA
+ # specification's names (v3.1 section 7.3.2.6 --
+ # matches values in section 4.3.6).
+ RNE = 0b00
+ """Round to Nearest Even
+
+ Rounds to the nearest representable floating-point number, ties are
+ rounded to the number with the even mantissa. Treats +-Infinity as if
+ it were a normalized floating-point number when deciding which number
+ is closer when rounding. See IEEE754 spec. for details.
+ """
+
+ ROUND_NEAREST_TIES_TO_EVEN = RNE
+ DEFAULT = RNE
+
+ RTZ = 0b01
+ """Round towards Zero
+
+ If the result is exactly representable as a floating-point number, return
+ that, otherwise return the nearest representable floating-point value
+ with magnitude smaller than the exact answer.
+ """
+
+ ROUND_TOWARDS_ZERO = RTZ
+
+ RTP = 0b10
+ """Round towards +Infinity
+
+ If the result is exactly representable as a floating-point number, return
+ that, otherwise return the nearest representable floating-point value
+ that is numerically greater than the exact answer. This can round up to
+ +Infinity.
+ """
+
+ ROUND_TOWARDS_POSITIVE = RTP
+
+ RTN = 0b11
+ """Round towards -Infinity
+
+ If the result is exactly representable as a floating-point number, return
+ that, otherwise return the nearest representable floating-point value
+ that is numerically less than the exact answer. This can round down to
+ -Infinity.
+ """
+
+ ROUND_TOWARDS_NEGATIVE = RTN
+
+ RNA = 0b100
+ """Round to Nearest Away
+
+ Rounds to the nearest representable floating-point number, ties are
+ rounded to the number with the maximum magnitude. Treats +-Infinity as if
+ it were a normalized floating-point number when deciding which number
+ is closer when rounding. See IEEE754 spec. for details.
+ """
+
+ ROUND_NEAREST_TIES_TO_AWAY = RNA
+
+ RTOP = 0b101
+ """Round to Odd, unsigned zeros are Positive
+
+ Not in smtlib2.
+
+ If the result is exactly representable as a floating-point number, return
+ that, otherwise return the nearest representable floating-point value
+ that has an odd mantissa.
+
+ If the result is zero but with otherwise undetermined sign
+ (e.g. `1.0 - 1.0`), the sign is positive.
+
+ This rounding mode is used for instructions with Round To Odd enabled,
+ and `FPSCR.RN != RTN`.
+
+ This is useful to avoid double-rounding errors when doing arithmetic in a
+ larger type (e.g. f128) but where the answer should be a smaller type
+ (e.g. f80).
+ """
+
+ ROUND_TO_ODD_UNSIGNED_ZEROS_ARE_POSITIVE = RTOP
+
+ RTON = 0b110
+ """Round to Odd, unsigned zeros are Negative
+
+ Not in smtlib2.
+
+ If the result is exactly representable as a floating-point number, return
+ that, otherwise return the nearest representable floating-point value
+ that has an odd mantissa.
+
+ If the result is zero but with otherwise undetermined sign
+ (e.g. `1.0 - 1.0`), the sign is negative.
+
+ This rounding mode is used for instructions with Round To Odd enabled,
+ and `FPSCR.RN == RTN`.
+
+ This is useful to avoid double-rounding errors when doing arithmetic in a
+ larger type (e.g. f128) but where the answer should be a smaller type
+ (e.g. f80).
+ """
+
+ ROUND_TO_ODD_UNSIGNED_ZEROS_ARE_NEGATIVE = RTON
+
+ @staticmethod
+ def make_array(f):
+ l = [None] * len(FPRoundingMode)
+ for rm in FPRoundingMode:
+ l[rm.value] = f(rm)
+ return Array(l)
+
+ def overflow_rounds_to_inf(self, sign):
+ """returns true if an overflow should round to `inf`,
+ false if it should round to `max_normal`
+ """
+ not_sign = ~sign if isinstance(sign, Value) else not sign
+ if self is FPRoundingMode.RNE:
+ return True
+ elif self is FPRoundingMode.RTZ:
+ return False
+ elif self is FPRoundingMode.RTP:
+ return not_sign
+ elif self is FPRoundingMode.RTN:
+ return sign
+ elif self is FPRoundingMode.RNA:
+ return True
+ elif self is FPRoundingMode.RTOP:
+ return False
+ else:
+ assert self is FPRoundingMode.RTON
+ return False
+
+ def underflow_rounds_to_zero(self, sign):
+ """returns true if an underflow should round to `zero`,
+ false if it should round to `min_denormal`
+ """
+ not_sign = ~sign if isinstance(sign, Value) else not sign
+ if self is FPRoundingMode.RNE:
+ return True
+ elif self is FPRoundingMode.RTZ:
+ return True
+ elif self is FPRoundingMode.RTP:
+ return sign
+ elif self is FPRoundingMode.RTN:
+ return not_sign
+ elif self is FPRoundingMode.RNA:
+ return True
+ elif self is FPRoundingMode.RTOP:
+ return False
+ else:
+ assert self is FPRoundingMode.RTON
+ return False
+
+ def zero_sign(self):
+ """which sign an exact zero result should have when it isn't
+ otherwise determined, e.g. for `1.0 - 1.0`.
+ """
+ if self is FPRoundingMode.RNE:
+ return False
+ elif self is FPRoundingMode.RTZ:
+ return False
+ elif self is FPRoundingMode.RTP:
+ return False
+ elif self is FPRoundingMode.RTN:
+ return True
+ elif self is FPRoundingMode.RNA:
+ return False
+ elif self is FPRoundingMode.RTOP:
+ return False
+ else:
+ assert self is FPRoundingMode.RTON
+ return True
+
+ if _HAVE_SMTLIB2:
+ def to_smtlib2(self, default=_raise_err):
+ """return the corresponding smtlib2 rounding mode for `self`. If
+ there is no corresponding smtlib2 rounding mode, then return
+ `default` if specified, else raise `ValueError`.
+ """
+ if self is FPRoundingMode.RNE:
+ return RoundingModeEnum.RNE
+ elif self is FPRoundingMode.RTZ:
+ return RoundingModeEnum.RTZ
+ elif self is FPRoundingMode.RTP:
+ return RoundingModeEnum.RTP
+ elif self is FPRoundingMode.RTN:
+ return RoundingModeEnum.RTN
+ elif self is FPRoundingMode.RNA:
+ return RoundingModeEnum.RNA
+ else:
+ assert self in (FPRoundingMode.RTOP, FPRoundingMode.RTON)
+ if default is _raise_err:
+ raise ValueError(
+ "no corresponding smtlib2 rounding mode", self)
+ return default
+
+
class FPFormat:
"""
return x & self.mantissa_mask
+ def get_mantissa_value(self, x):
+ """ returns the mantissa of its input number, x, but with the
+ implicit bit, if any, made explicit.
+ """
+ if self.has_int_bit:
+ return self.get_mantissa_field(x)
+ exponent_field = self.get_exponent_field(x)
+ mantissa_field = self.get_mantissa_field(x)
+ implicit_bit = exponent_field == self.exponent_denormal_zero
+ return (implicit_bit << self.fraction_width) | mantissa_field
+
def is_zero(self, x):
""" returns true if x is +/- zero
"""
- return (self.get_exponent(x) == self.e_sub and
- self.get_mantissa_field(x) == 0)
+ return (self.get_exponent(x) == self.e_sub) & \
+ (self.get_mantissa_field(x) == 0)
def is_subnormal(self, x):
""" returns true if x is subnormal (exp at minimum)
"""
- return (self.get_exponent(x) == self.e_sub and
- self.get_mantissa_field(x) != 0)
+ return (self.get_exponent(x) == self.e_sub) & \
+ (self.get_mantissa_field(x) != 0)
def is_inf(self, x):
""" returns true if x is infinite
"""
- return (self.get_exponent(x) == self.e_max and
- self.get_mantissa_field(x) == 0)
+ return (self.get_exponent(x) == self.e_max) & \
+ (self.get_mantissa_field(x) == 0)
def is_nan(self, x):
""" returns true if x is a nan (quiet or signalling)
"""
- return (self.get_exponent(x) == self.e_max and
- self.get_mantissa_field(x) != 0)
+ return (self.get_exponent(x) == self.e_max) & \
+ (self.get_mantissa_field(x) != 0)
def is_quiet_nan(self, x):
""" returns true if x is a quiet nan
"""
- highbit = 1<<(self.m_width-1)
- return (self.get_exponent(x) == self.e_max and
- self.get_mantissa_field(x) != 0 and
- self.get_mantissa_field(x) & highbit != 0)
+ highbit = 1 << (self.m_width - 1)
+ return (self.get_exponent(x) == self.e_max) & \
+ (self.get_mantissa_field(x) != 0) & \
+ (self.get_mantissa_field(x) & highbit != 0)
+
+ def to_quiet_nan(self, x):
+ """ converts `x` to a quiet NaN """
+ highbit = 1 << (self.m_width - 1)
+ return x | highbit | self.exponent_mask
+
+ def quiet_nan(self, sign=0):
+ """ return the default quiet NaN with sign `sign` """
+ return self.to_quiet_nan(self.zero(sign))
+
+ def zero(self, sign=0):
+ """ return zero with sign `sign` """
+ return (sign != 0) << (self.e_width + self.m_width)
+
+ def inf(self, sign=0):
+ """ return infinity with sign `sign` """
+ return self.zero(sign) | self.exponent_mask
def is_nan_signaling(self, x):
""" returns true if x is a signalling nan
"""
- highbit = 1<<(self.m_width-1)
- return ((self.get_exponent(x) == self.e_max) and
- (self.get_mantissa_field(x) != 0) and
- (self.get_mantissa_field(x) & highbit) == 0)
+ highbit = 1 << (self.m_width - 1)
+ return (self.get_exponent(x) == self.e_max) & \
+ (self.get_mantissa_field(x) != 0) & \
+ (self.get_mantissa_field(x) & highbit) == 0
@property
def width(self):
""" Get a mantissa mask based on the mantissa width """
return (1 << self.m_width) - 1
+ @property
+ def exponent_mask(self):
+ """ Get an exponent mask """
+ return self.exponent_inf_nan << self.m_width
+
@property
def exponent_inf_nan(self):
""" Get the value of the exponent field designating infinity/NaN. """
f32.get_mantissa_field(x), i)
self.assertEqual(i, True)
+
class MultiShiftR:
def __init__(self, width):
class FPNumBaseRecord:
- """ Floating-point Base Number Class
+ """ Floating-point Base Number Class.
+
+ This class is designed to be passed around in other data structures
+ (between pipelines and between stages). Its "friend" is FPNumBase,
+ which is a *module*. The reason for the discernment is because
+ nmigen modules that are not added to submodules results in the
+ irritating "Elaboration" warning. Despite not *needing* FPNumBase
+ in many cases to be added as a submodule (because it is just data)
+ this was not possible to solve without splitting out the data from
+ the module.
"""
def __init__(self, width, m_extra=True, e_extra=False, name=None):
def nan(self, s):
return self.create(*self._nan(s))
+ def quieted_nan(self, other):
+ assert isinstance(other, FPNumBaseRecord)
+ assert self.width == other.width
+ return self.create(other.s, self.fp.P128,
+ other.v[0:self.e_start] | (1 << (self.e_start - 1)))
+
def inf(self, s):
return self.create(*self._inf(s))
+ def max_normal(self, s):
+ return self.create(s, self.fp.P127, ~0)
+
+ def min_denormal(self, s):
+ return self.create(s, self.fp.N127, 1)
+
def zero(self, s):
return self.create(*self._zero(s))
def __init__(self, width, s_max=None):
if s_max is None:
s_max = int(log(width) / log(2))
- self.smax = s_max
+ self.smax = Shape.cast(s_max)
self.m = Signal(width, reset_less=True)
self.inp = Signal(width, reset_less=True)
self.diff = Signal(s_max, reset_less=True)
m_mask = Signal(self.width, reset_less=True)
smask = Signal(self.width, reset_less=True)
stickybit = Signal(reset_less=True)
- maxslen = Signal(self.smax, reset_less=True)
- maxsleni = Signal(self.smax, reset_less=True)
+ # XXX GRR frickin nuisance https://github.com/nmigen/nmigen/issues/302
+ maxslen = Signal(self.smax.width, reset_less=True)
+ maxsleni = Signal(self.smax.width, reset_less=True)
sm = MultiShift(self.width-1)
m0s = Const(0, self.width-1)
]
-class Overflow: # (Elaboratable):
+class Overflow:
+ # TODO: change FFLAGS to be FPSCR's status flags
+ FFLAGS_NV = Const(1<<4, 5) # invalid operation
+ FFLAGS_DZ = Const(1<<3, 5) # divide by zero
+ FFLAGS_OF = Const(1<<2, 5) # overflow
+ FFLAGS_UF = Const(1<<1, 5) # underflow
+ FFLAGS_NX = Const(1<<0, 5) # inexact
def __init__(self, name=None):
if name is None:
name = ""
self.round_bit = Signal(reset_less=True, name=name+"round") # tot[1]
self.sticky = Signal(reset_less=True, name=name+"sticky") # tot[0]
self.m0 = Signal(reset_less=True, name=name+"m0") # mantissa bit 0
+ self.fpflags = Signal(5, reset_less=True, name=name+"fflags")
+
+ self.sign = Signal(reset_less=True, name=name+"sign")
+ """sign bit -- 1 means negative, 0 means positive"""
+
+ self.rm = Signal(FPRoundingMode, name=name+"rm",
+ reset=FPRoundingMode.DEFAULT)
+ """rounding mode"""
#self.roundz = Signal(reset_less=True)
yield self.round_bit
yield self.sticky
yield self.m0
+ yield self.fpflags
+ yield self.sign
+ yield self.rm
def eq(self, inp):
return [self.guard.eq(inp.guard),
self.round_bit.eq(inp.round_bit),
self.sticky.eq(inp.sticky),
- self.m0.eq(inp.m0)]
+ self.m0.eq(inp.m0),
+ self.fpflags.eq(inp.fpflags),
+ self.sign.eq(inp.sign),
+ self.rm.eq(inp.rm)]
@property
- def roundz(self):
+ def roundz_rne(self):
+ """true if the mantissa should be rounded up for `rm == RNE`
+
+ assumes the rounding mode is `ROUND_NEAREST_TIES_TO_EVEN`
+ """
return self.guard & (self.round_bit | self.sticky | self.m0)
+ @property
+ def roundz_rna(self):
+ """true if the mantissa should be rounded up for `rm == RNA`
+
+ assumes the rounding mode is `ROUND_NEAREST_TIES_TO_AWAY`
+ """
+ return self.guard
+
+ @property
+ def roundz_rtn(self):
+ """true if the mantissa should be rounded up for `rm == RTN`
+
+ assumes the rounding mode is `ROUND_TOWARDS_NEGATIVE`
+ """
+ return self.sign & (self.guard | self.round_bit | self.sticky)
+
+ @property
+ def roundz_rto(self):
+ """true if the mantissa should be rounded up for `rm in (RTOP, RTON)`
+
+ assumes the rounding mode is `ROUND_TO_ODD_UNSIGNED_ZEROS_ARE_POSITIVE`
+ or `ROUND_TO_ODD_UNSIGNED_ZEROS_ARE_NEGATIVE`
+ """
+ return ~self.m0 & (self.guard | self.round_bit | self.sticky)
+
+ @property
+ def roundz_rtp(self):
+ """true if the mantissa should be rounded up for `rm == RTP`
+
+ assumes the rounding mode is `ROUND_TOWARDS_POSITIVE`
+ """
+ return ~self.sign & (self.guard | self.round_bit | self.sticky)
+
+ @property
+ def roundz_rtz(self):
+ """true if the mantissa should be rounded up for `rm == RTZ`
+
+ assumes the rounding mode is `ROUND_TOWARDS_ZERO`
+ """
+ return False
+
+ @property
+ def roundz(self):
+ """true if the mantissa should be rounded up for the current rounding
+ mode `self.rm`
+ """
+ d = {
+ FPRoundingMode.RNA: self.roundz_rna,
+ FPRoundingMode.RNE: self.roundz_rne,
+ FPRoundingMode.RTN: self.roundz_rtn,
+ FPRoundingMode.RTOP: self.roundz_rto,
+ FPRoundingMode.RTON: self.roundz_rto,
+ FPRoundingMode.RTP: self.roundz_rtp,
+ FPRoundingMode.RTZ: self.roundz_rtz,
+ }
+ return FPRoundingMode.make_array(lambda rm: d[rm])[self.rm]
+
class OverflowMod(Elaboratable, Overflow):
def __init__(self, name=None):
def elaborate(self, platform):
m = Module()
- m.d.comb += self.roundz_out.eq(self.roundz)
+ m.d.comb += self.roundz_out.eq(self.roundz) # roundz is a property
return m
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