from nmigen.cli import main, verilog
from math import log
-from nmutil.pipemodbase import FPModBase
+from nmutil.pipemodbase import PipeModBase
from ieee754.fpcommon.fpbase import (Overflow, OverflowMod,
FPNumBase, FPNumBaseRecord)
from ieee754.fpcommon.fpbase import FPState
from ieee754.fpcommon.getop import FPPipeContext
from ieee754.fpcommon.msbhigh import FPMSBHigh
from ieee754.fpcommon.exphigh import FPEXPHigh
-from ieee754.fpcommon.postcalc import FPAddStage1Data
+from ieee754.fpcommon.postcalc import FPPostCalcData
class FPNorm1Data:
return ret
-class FPNorm1ModSingle(FPModBase):
+class FPNorm1ModSingle(PipeModBase):
def __init__(self, pspec, e_extra=False):
self.e_extra = e_extra
super().__init__(pspec, "normalise_1")
def ispec(self):
- return FPAddStage1Data(self.pspec, e_extra=self.e_extra)
+ return FPPostCalcData(self.pspec, e_extra=self.e_extra)
def ospec(self):
return FPNorm1Data(self.pspec)
def elaborate(self, platform):
m = Module()
- of = OverflowMod("norm1of_")
-
- #m.submodules.norm1_out_z = self.o.z
- m.submodules.norm1_out_overflow = of
- #m.submodules.norm1_in_z = self.i.z
- #m.submodules.norm1_in_overflow = self.i.of
+ m.submodules.norm1_out_overflow = of = OverflowMod("norm1of_")
i = self.ispec()
i.of.guard.name = "norm1_i_of_guard"
i.of.sticky.name = "norm1_i_of_sticky"
i.of.m0.name = "norm1_i_of_m0"
m.submodules.norm1_insel_z = insel_z = FPNumBase(i.z)
- #m.submodules.norm1_insel_overflow = iof = OverflowMod("iof")
espec = (len(insel_z.e), True)
mwid = self.o.z.m_width+2
# initialise out from in (overridden below)
m.d.comb += self.o.z.eq(insel_z)
m.d.comb += Overflow.eq(of, i.of)
+
# normalisation increase/decrease conditions
decrease = Signal(reset_less=True)
increase = Signal(reset_less=True)
m.d.comb += decrease.eq(insel_z.m_msbzero & insel_z.exp_gt_n126)
m.d.comb += increase.eq(insel_z.exp_lt_n126)
+
+ # concatenate s/r/g with mantissa. (it was easier to do this
+ # than to have the mantissa contain the three extra bits)
+ temp_m = Signal(mwid+2, reset_less=True)
+ m.d.comb += temp_m.eq(Cat(i.of.sticky, i.of.round_bit, i.of.guard,
+ insel_z.m)),
+
# decrease exponent
- with m.If(~self.i.out_do_z):
- # concatenate s/r/g with mantissa
- temp_m = Signal(mwid+2, reset_less=True)
- m.d.comb += temp_m.eq(Cat(i.of.sticky, i.of.round_bit, i.of.guard,
- insel_z.m)),
-
- with m.If(decrease):
- # make sure that the amount to decrease by does NOT
- # go below the minimum non-INF/NaN exponent
- m.d.comb += msb.limclz.eq(insel_z.exp_sub_n126)
- m.d.comb += [
- # inputs: mantissa and exponent
- msb.m_in.eq(temp_m),
- msb.e_in.eq(insel_z.e),
-
- # outputs: mantissa first (s/r/g/m[3:])
- self.o.z.m.eq(msb.m_out[3:]), # exclude bits 0&1
- of.m0.eq(msb.m_out[3]), # copy of mantissa[0]
- # overflow in bits 0..1: got shifted too (leave sticky)
- of.guard.eq(msb.m_out[2]), # guard
- of.round_bit.eq(msb.m_out[1]), # round
- # now exponent out
- self.o.z.e.eq(msb.e_out),
- ]
- # increase exponent
- with m.Elif(increase):
- ediff_n126 = Signal(espec, reset_less=True)
- m.d.comb += [
- # concatenate
- ediff_n126.eq(insel_z.fp.N126 - insel_z.e),
- # connect multi-shifter to inp/out m/e (and ediff)
- msr.m_in.eq(temp_m),
- msr.e_in.eq(insel_z.e),
- msr.ediff.eq(ediff_n126),
-
- # outputs: mantissa first (s/r/g/m[3:])
- self.o.z.m.eq(msr.m_out[3:]),
- of.m0.eq(msr.m_out[3]), # copy of mantissa[0]
- # overflow in bits 0..2: got shifted too (leave sticky)
- of.guard.eq(msr.m_out[2]), # guard
- of.round_bit.eq(msr.m_out[1]), # round
- of.sticky.eq(msr.m_out[0]), # sticky
- # now exponent
- self.o.z.e.eq(msr.e_out),
- ]
+ with m.If(decrease):
+ # make sure that the amount to decrease by does NOT
+ # go below the minimum non-INF/NaN exponent
+ m.d.comb += msb.limclz.eq(insel_z.exp_sub_n126)
+ m.d.comb += [
+ # inputs: mantissa and exponent
+ msb.m_in.eq(temp_m),
+ msb.e_in.eq(insel_z.e),
+
+ # outputs: mantissa first (s/r/g/m[3:])
+ self.o.z.m.eq(msb.m_out[3:]), # exclude bits 0&1
+ of.m0.eq(msb.m_out[3]), # copy of mantissa[0]
+ # overflow in bits 0..1: got shifted too (leave sticky)
+ of.guard.eq(msb.m_out[2]), # guard
+ of.round_bit.eq(msb.m_out[1]), # round
+ # now exponent out
+ self.o.z.e.eq(msb.e_out),
+ ]
+ # increase exponent
+ with m.Elif(increase):
+ ediff_n126 = Signal(espec, reset_less=True)
+ m.d.comb += [
+ # concatenate
+ ediff_n126.eq(insel_z.fp.N126 - insel_z.e),
+ # connect multi-shifter to inp/out m/e (and ediff)
+ msr.m_in.eq(temp_m),
+ msr.e_in.eq(insel_z.e),
+ msr.ediff.eq(ediff_n126),
+
+ # outputs: mantissa first (s/r/g/m[3:])
+ self.o.z.m.eq(msr.m_out[3:]),
+ of.m0.eq(msr.m_out[3]), # copy of mantissa[0]
+ # overflow in bits 0..2: got shifted too (leave sticky)
+ of.guard.eq(msr.m_out[2]), # guard
+ of.round_bit.eq(msr.m_out[1]), # round
+ of.sticky.eq(msr.m_out[0]), # sticky
+ # now exponent
+ self.o.z.e.eq(msr.e_out),
+ ]
m.d.comb += self.o.roundz.eq(of.roundz_out)
m.d.comb += self.o.ctx.eq(self.i.ctx)
projects / ieee754fpu.git / blobdiff