# Copyright (C) Jonathan P Dawson 2013
# 2013-12-12
-from nmigen import Module, Signal, Cat, Mux, Elaboratable
-from nmigen.lib.coding import PriorityEncoder
+from nmigen import Module, Signal, Cat, Mux
from nmigen.cli import main, verilog
from math import log
-from fpbase import Overflow, FPNumBase
-from fpbase import MultiShiftRMerge
-from fpbase import FPState
-from .postcalc import FPAddStage1Data
+from nmutil.pipemodbase import PipeModBase
+from ieee754.fpcommon.fpbase import (Overflow, OverflowMod,
+ FPNumBase, FPNumBaseRecord)
+from ieee754.fpcommon.fpbase import FPState
+from ieee754.fpcommon.getop import FPPipeContext
+from ieee754.fpcommon.msbhigh import FPMSBHigh
+from ieee754.fpcommon.exphigh import FPEXPHigh
+from ieee754.fpcommon.postcalc import FPPostCalcData
class FPNorm1Data:
- def __init__(self, width, id_wid):
- self.roundz = Signal(reset_less=True)
- self.z = FPNumBase(width, False)
+ def __init__(self, pspec):
+ width = pspec.width
+ self.roundz = Signal(reset_less=True, name="norm1_roundz")
+ self.z = FPNumBaseRecord(width, False, name="z")
self.out_do_z = Signal(reset_less=True)
self.oz = Signal(width, reset_less=True)
- self.mid = Signal(id_wid, reset_less=True)
+ self.ctx = FPPipeContext(pspec)
+ self.muxid = self.ctx.muxid
def eq(self, i):
- return [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz),
- self.roundz.eq(i.roundz), self.mid.eq(i.mid)]
+ ret = [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz),
+ self.roundz.eq(i.roundz), self.ctx.eq(i.ctx)]
+ return ret
-class FPNorm1ModSingle(Elaboratable):
+class FPNorm1ModSingle(PipeModBase):
- def __init__(self, width, id_wid):
- self.width = width
- self.id_wid = id_wid
- self.i = self.ispec()
- self.o = self.ospec()
+ def __init__(self, pspec, e_extra=False):
+ self.e_extra = e_extra
+ super().__init__(pspec, "normalise_1")
def ispec(self):
- return FPAddStage1Data(self.width, self.id_wid)
+ return FPPostCalcData(self.pspec, e_extra=self.e_extra)
def ospec(self):
- return FPNorm1Data(self.width, self.id_wid)
-
- def setup(self, m, i):
- """ links module to inputs and outputs
- """
- m.submodules.normalise_1 = self
- m.d.comb += self.i.eq(i)
-
- def process(self, i):
- return self.o
+ return FPNorm1Data(self.pspec)
def elaborate(self, platform):
m = Module()
- mwid = self.o.z.m_width+2
- pe = PriorityEncoder(mwid)
- m.submodules.norm_pe = pe
+ m.submodules.norm1_out_overflow = of = OverflowMod("norm1of_")
- of = Overflow()
- m.d.comb += self.o.roundz.eq(of.roundz)
+ i = self.ispec()
+ i.of.guard.name = "norm1_i_of_guard"
+ i.of.round_bit.name = "norm1_i_of_roundbit"
+ i.of.sticky.name = "norm1_i_of_sticky"
+ i.of.m0.name = "norm1_i_of_m0"
+ m.submodules.norm1_insel_z = insel_z = FPNumBase(i.z)
- m.submodules.norm1_out_z = self.o.z
- m.submodules.norm1_out_overflow = of
- m.submodules.norm1_in_z = self.i.z
- m.submodules.norm1_in_overflow = self.i.of
+ espec = (len(insel_z.e), True)
+ mwid = self.o.z.m_width+2
- i = self.ispec()
- m.submodules.norm1_insel_z = i.z
- m.submodules.norm1_insel_overflow = i.of
+ msr = FPEXPHigh(mwid+2, espec[0])
+ m.submodules.norm_exp = msr
- espec = (len(i.z.e), True)
- ediff_n126 = Signal(espec, reset_less=True)
- msr = MultiShiftRMerge(mwid, espec)
- m.submodules.multishift_r = msr
+ msb = FPMSBHigh(mwid+1, espec[0], True)
+ m.submodules.norm_msb = msb
m.d.comb += i.eq(self.i)
# initialise out from in (overridden below)
- m.d.comb += self.o.z.eq(i.z)
- m.d.comb += of.eq(i.of)
+ m.d.comb += self.o.z.eq(insel_z)
+ m.d.comb += Overflow.eq(of, i.of)
+
# normalisation increase/decrease conditions
decrease = Signal(reset_less=True)
increase = Signal(reset_less=True)
- m.d.comb += decrease.eq(i.z.m_msbzero & i.z.exp_gt_n126)
- m.d.comb += increase.eq(i.z.exp_lt_n126)
+ m.d.comb += decrease.eq(insel_z.m_msbzero & insel_z.exp_gt_n126)
+ m.d.comb += increase.eq(insel_z.exp_lt_n126)
+
+ # concatenate s/r/g with mantissa. (it was easier to do this
+ # than to have the mantissa contain the three extra bits)
+ temp_m = Signal(mwid+2, reset_less=True)
+ m.d.comb += temp_m.eq(Cat(i.of.sticky, i.of.round_bit, i.of.guard,
+ insel_z.m)),
+
# decrease exponent
- with m.If(~self.i.out_do_z):
- with m.If(decrease):
- # *sigh* not entirely obvious: count leading zeros (clz)
- # with a PriorityEncoder: to find from the MSB
- # we reverse the order of the bits.
- temp_m = Signal(mwid, reset_less=True)
- temp_s = Signal(mwid+1, reset_less=True)
- clz = Signal((len(i.z.e), True), reset_less=True)
- # make sure that the amount to decrease by does NOT
- # go below the minimum non-INF/NaN exponent
- limclz = Mux(i.z.exp_sub_n126 > pe.o, pe.o,
- i.z.exp_sub_n126)
- m.d.comb += [
- # cat round and guard bits back into the mantissa
- temp_m.eq(Cat(i.of.round_bit, i.of.guard, i.z.m)),
- pe.i.eq(temp_m[::-1]), # inverted
- clz.eq(limclz), # count zeros from MSB down
- temp_s.eq(temp_m << clz), # shift mantissa UP
- self.o.z.e.eq(i.z.e - clz), # DECREASE exponent
- self.o.z.m.eq(temp_s[2:]), # exclude bits 0&1
- of.m0.eq(temp_s[2]), # copy of mantissa[0]
- # overflow in bits 0..1: got shifted too (leave sticky)
- of.guard.eq(temp_s[1]), # guard
- of.round_bit.eq(temp_s[0]), # round
- ]
- # increase exponent
- with m.Elif(increase):
- temp_m = Signal(mwid+1, reset_less=True)
- m.d.comb += [
- temp_m.eq(Cat(i.of.sticky, i.of.round_bit, i.of.guard,
- i.z.m)),
- ediff_n126.eq(i.z.N126 - i.z.e),
- # connect multi-shifter to inp/out mantissa (and ediff)
- msr.inp.eq(temp_m),
- msr.diff.eq(ediff_n126),
- self.o.z.m.eq(msr.m[3:]),
- of.m0.eq(temp_s[3]), # copy of mantissa[0]
- # overflow in bits 0..1: got shifted too (leave sticky)
- of.guard.eq(temp_s[2]), # guard
- of.round_bit.eq(temp_s[1]), # round
- of.sticky.eq(temp_s[0]), # sticky
- self.o.z.e.eq(i.z.e + ediff_n126),
- ]
+ with m.If(decrease):
+ # make sure that the amount to decrease by does NOT
+ # go below the minimum non-INF/NaN exponent
+ m.d.comb += msb.limclz.eq(insel_z.exp_sub_n126)
+ m.d.comb += [
+ # inputs: mantissa and exponent
+ msb.m_in.eq(temp_m),
+ msb.e_in.eq(insel_z.e),
+
+ # outputs: mantissa first (s/r/g/m[3:])
+ self.o.z.m.eq(msb.m_out[3:]), # exclude bits 0&1
+ of.m0.eq(msb.m_out[3]), # copy of mantissa[0]
+ # overflow in bits 0..1: got shifted too (leave sticky)
+ of.guard.eq(msb.m_out[2]), # guard
+ of.round_bit.eq(msb.m_out[1]), # round
+ # now exponent out
+ self.o.z.e.eq(msb.e_out),
+ ]
+ # increase exponent
+ with m.Elif(increase):
+ ediff_n126 = Signal(espec, reset_less=True)
+ m.d.comb += [
+ # concatenate
+ ediff_n126.eq(insel_z.fp.N126 - insel_z.e),
+ # connect multi-shifter to inp/out m/e (and ediff)
+ msr.m_in.eq(temp_m),
+ msr.e_in.eq(insel_z.e),
+ msr.ediff.eq(ediff_n126),
+
+ # outputs: mantissa first (s/r/g/m[3:])
+ self.o.z.m.eq(msr.m_out[3:]),
+ of.m0.eq(msr.m_out[3]), # copy of mantissa[0]
+ # overflow in bits 0..2: got shifted too (leave sticky)
+ of.guard.eq(msr.m_out[2]), # guard
+ of.round_bit.eq(msr.m_out[1]), # round
+ of.sticky.eq(msr.m_out[0]), # sticky
+ # now exponent
+ self.o.z.e.eq(msr.e_out),
+ ]
- m.d.comb += self.o.mid.eq(self.i.mid)
+ m.d.comb += self.o.roundz.eq(of.roundz_out)
+ m.d.comb += self.o.ctx.eq(self.i.ctx)
m.d.comb += self.o.out_do_z.eq(self.i.out_do_z)
m.d.comb += self.o.oz.eq(self.i.oz)
class FPNorm1ModMulti:
- def __init__(self, width, single_cycle=True):
+ def __init__(self, pspec, single_cycle=True):
self.width = width
self.in_select = Signal(reset_less=True)
self.in_z = FPNumBase(width, False)
increase = Signal(reset_less=True)
m.d.comb += decrease.eq(in_z.m_msbzero & in_z.exp_gt_n126)
m.d.comb += increase.eq(in_z.exp_lt_n126)
- m.d.comb += self.out_norm.eq(decrease | increase) # loop-end
+ m.d.comb += self.out_norm.eq(decrease | increase) # loop-end
# decrease exponent
with m.If(decrease):
m.d.comb += [
self.out_z.e.eq(in_z.e - 1), # DECREASE exponent
- self.out_z.m.eq(in_z.m << 1), # shift mantissa UP
- self.out_z.m[0].eq(in_of.guard), # steal guard (was tot[2])
- self.out_of.guard.eq(in_of.round_bit), # round (was tot[1])
+ self.out_z.m.eq(in_z.m << 1), # shift mantissa UP
+ self.out_z.m[0].eq(in_of.guard), # steal guard (was tot[2])
+ self.out_of.guard.eq(in_of.round_bit), # round (was tot[1])
self.out_of.round_bit.eq(0), # reset round bit
self.out_of.m0.eq(in_of.guard),
]
with m.Elif(increase):
m.d.comb += [
self.out_z.e.eq(in_z.e + 1), # INCREASE exponent
- self.out_z.m.eq(in_z.m >> 1), # shift mantissa DOWN
+ self.out_z.m.eq(in_z.m >> 1), # shift mantissa DOWN
self.out_of.guard.eq(in_z.m[0]),
self.out_of.m0.eq(in_z.m[1]),
self.out_of.round_bit.eq(in_of.guard),
self.out_z, self.out_norm)
m.d.comb += self.stb.eq(norm_stb)
- m.d.sync += self.ack.eq(0) # sets to zero when not in normalise_1 state
+ # sets to zero when not in normalise_1 state
+ m.d.sync += self.ack.eq(0)
def action(self, m):
m.d.comb += self.in_accept.eq((~self.ack) & (self.stb))
m.next = "round"
m.d.sync += self.ack.eq(1)
m.d.sync += self.out_roundz.eq(self.mod.out_of.roundz)
-
-
projects / ieee754fpu.git / blobdiff