more random experimenting

[ieee754fpu.git] / src / ieee754 / fpdiv / div0.py

diff --git a/src/ieee754/fpdiv/div0.py b/src/ieee754/fpdiv/div0.py
index 7b1d24f473aa09fe842205feac9ef5296051c078..1174d01b9618c9a8a27c7b8d696c121c51cdb938 100644 (file)
--- a/src/ieee754/fpdiv/div0.py
+++ b/src/ieee754/fpdiv/div0.py
@@ -65,15 +65,15 @@ class FPDivStage0Mod(Elaboratable):
             am0 = Signal(len(self.i.a.m)+3, reset_less=True)
             bm0 = Signal(len(self.i.b.m)+3, reset_less=True)
             m.d.comb += [
-                         am0.eq(Cat(0, 0, self.i.a.m, 0)),
-                         bm0.eq(Cat(0, 0, self.i.b.m, 0)),
+                         am0.eq(Cat(0,0,0,self.i.a.m, 0)),
+                         bm0.eq(Cat(0,0,0,self.i.b.m, 0)),
                          #am0.eq(0x392),
                          #bm0.eq(0x1110),
                         ]
 
             m.d.comb += [self.o.z.e.eq(self.i.a.e - self.i.b.e + 1),
                          self.o.z.s.eq(self.i.a.s ^ self.i.b.s),
-                         self.o.dividend[len(self.i.a.m):].eq(am0), # TODO: check
+                         self.o.dividend[len(self.i.a.m)+3:].eq(am0), # TODO: check
                          self.o.divisor_radicand.eq(bm0), # TODO: check
                          self.o.operation.eq(Const(0)) # TODO check: DIV
                 ]