big (single-purpose) update: move width arg into pspec

[ieee754fpu.git] / src / ieee754 / fpdiv / div1.py

diff --git a/src/ieee754/fpdiv/div1.py b/src/ieee754/fpdiv/div1.py
index 27e4b782328708f4f56032e7d94d4c46fd90b137..6cf49aba062b9ee73e8587c8f3d622ed83be09a7 100644 (file)
--- a/src/ieee754/fpdiv/div1.py
+++ b/src/ieee754/fpdiv/div1.py
@@ -14,19 +14,18 @@ from .div0 import FPDivStage0Data # TODO: replace with DivPipeCoreInterstageData
 
 class FPDivStage1Mod(Elaboratable):
 
-    def __init__(self, width, pspec):
-        self.width = width
+    def __init__(self, pspec):
         self.pspec = pspec
         self.i = self.ispec()
         self.o = self.ospec()
 
     def ispec(self):
         # TODO: DivPipeCoreInterstageData, here
-        return FPDivStage0Data(self.width, self.pspec) # Q/Rem (etc) in...
+        return FPDivStage0Data(self.pspec) # Q/Rem (etc) in...
 
     def ospec(self):
         # TODO: DivPipeCoreInterstageData, here
-        return FPDivStage0Data(self.width, self.pspec) # ... Q/Rem (etc) out
+        return FPDivStage0Data(self.pspec) # ... Q/Rem (etc) out
 
     def process(self, i):
         return self.o