convert fpdiv to pspec

[ieee754fpu.git] / src / ieee754 / fpdiv / div2.py

diff --git a/src/ieee754/fpdiv/div2.py b/src/ieee754/fpdiv/div2.py
index 6b9be39c4da67405551e4df7e51286be1c71fa3a..9c77667a604dba1817c62a7ecf922c77bd20889c 100644 (file)
--- a/src/ieee754/fpdiv/div2.py
+++ b/src/ieee754/fpdiv/div2.py
@@ -15,17 +15,17 @@ class FPDivStage2Mod(FPState, Elaboratable):
     """ Second stage of div: preparation for normalisation.
     """
 
-    def __init__(self, width, id_wid):
+    def __init__(self, width, pspec):
         self.width = width
-        self.id_wid = id_wid
+        self.pspec = pspec
         self.i = self.ispec()
         self.o = self.ospec()
 
     def ispec(self):
-        return FPDivStage0Data(self.width, self.id_wid) # Q/Rem in...
+        return FPDivStage0Data(self.width, self.pspec) # Q/Rem in...
 
     def ospec(self):
-        return FPAddStage1Data(self.width, self.id_wid) # out to post-process
+        return FPAddStage1Data(self.width, self.pspec) # out to post-process
 
     def process(self, i):
         return self.o
@@ -50,6 +50,9 @@ class FPDivStage2Mod(FPState, Elaboratable):
         # last-stage guard/round/sticky and copies mantissa into z.
         # post-processing stages take care of things from that point.
 
+        # NOTE: this phase does NOT do ACTUAL DIV processing, it ONLY
+        # does "conversion" *out* of the Q/REM last stage
+
         with m.If(~self.i.out_do_z):
             mw = self.o.z.m_width
             m.d.comb += [
@@ -62,14 +65,14 @@ class FPDivStage2Mod(FPState, Elaboratable):
 
         m.d.comb += self.o.out_do_z.eq(self.i.out_do_z)
         m.d.comb += self.o.oz.eq(self.i.oz)
-        m.d.comb += self.o.mid.eq(self.i.mid)
+        m.d.comb += self.o.ctx.eq(self.i.ctx)
 
         return m
 
 
 class FPDivStage2(FPState):
 
-    def __init__(self, width, id_wid):
+    def __init__(self, width, pspec):
         FPState.__init__(self, "divider_1")
         self.mod = FPDivStage2Mod(width)
         self.out_z = FPNumBaseRecord(width, False)