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[ieee754fpu.git] / src / ieee754 / fpdiv / pipeline.py

diff --git a/src/ieee754/fpdiv/pipeline.py b/src/ieee754/fpdiv/pipeline.py
index 278e180431da7bcaa04b67f241aacf46bb5a495b..6a9cf809d626a7f946fb4a67b2c11bc36280b338 100644 (file)
--- a/src/ieee754/fpdiv/pipeline.py
+++ b/src/ieee754/fpdiv/pipeline.py
@@ -1,10 +1,16 @@
-"""IEEE Floating Point Divider Pipeline
+"""IEEE754 Floating Point Divider Pipeline
 
-Relevant bugreport: http://bugs.libre-riscv.org/show_bug.cgi?id=99
+Copyright (C) 2019 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Copyright (C) 2019 Jacob Lifshay
+
+Relevant bugreports:
+* http://bugs.libre-riscv.org/show_bug.cgi?id=99
+* http://bugs.libre-riscv.org/show_bug.cgi?id=43
+* http://bugs.libre-riscv.org/show_bug.cgi?id=44
 
 Stack looks like this:
 
-scnorm   - FPDIVSpecialCasesDeNorm ispec FPADDBaseData
+scnorm   - FPDIVSpecialCasesDeNorm ispec FPBaseData
 ------                             ospec FPSCData
 
                 StageChain: FPDIVSpecialCasesMod,
@@ -13,7 +19,7 @@ scnorm   - FPDIVSpecialCasesDeNorm ispec FPADDBaseData
 pipediv0 - FPDivStagesSetup        ispec FPSCData
 --------                           ospec DivPipeInterstageData
 
-                StageChain: FPDivStage0Mod,
+                StageChain: FPDivPreFPAdjust,
                             DivPipeSetupStage,
                             DivPipeCalculateStage,
                             ...
@@ -29,15 +35,15 @@ pipediv1 - FPDivStagesIntermediate ispec DivPipeInterstageData
 ...
 
 pipediv5 - FPDivStageFinal         ispec FPDivStage0Data
---------                           ospec FPAddStage1Data
+--------                           ospec FPPostCalcData
 
                 StageChain: DivPipeCalculateStage,
                             ...
                             DivPipeCalculateStage,
                             DivPipeFinalStage,
-                            FPDivStage2Mod
+                            FPDivPostToFPFormat
 
-normpack - FPNormToPack            ispec FPAddStage1Data
+normpack - FPNormToPack            ispec FPPostCalcData
 --------                           ospec FPPackData
 
                 StageChain: Norm1ModSingle,
@@ -57,16 +63,10 @@ RS's.  that's far too many.  6 is just about an acceptable number.
 even 8 is starting to get alarmingly high.
 """
 
-from nmigen import Module
-from nmigen.cli import main, verilog
-
 from nmutil.singlepipe import ControlBase
 from nmutil.concurrentunit import ReservationStations, num_bits
 
-from ieee754.fpcommon.getop import FPADDBaseData
-from ieee754.fpcommon.denorm import FPSCData
 from ieee754.fpcommon.fpbase import FPFormat
-from ieee754.fpcommon.pack import FPPackData
 from ieee754.fpcommon.normtopack import FPNormToPack
 from ieee754.fpdiv.specialcases import FPDIVSpecialCasesDeNorm
 from ieee754.fpdiv.divstages import (FPDivStagesSetup,
@@ -74,12 +74,13 @@ from ieee754.fpdiv.divstages import (FPDivStagesSetup,
                                      FPDivStagesFinal)
 from ieee754.pipeline import PipelineSpec
 from ieee754.div_rem_sqrt_rsqrt.core import DivPipeCoreConfig
+from nmutil.dynamicpipe import MaskCancellableRedir
 
 
 class FPDIVBasePipe(ControlBase):
     def __init__(self, pspec):
         self.pspec = pspec
-        ControlBase.__init__(self)
+        ControlBase.__init__(self, maskwid=pspec.maskwid)
 
         pipechain = []
         # to which the answer: "as few as possible"
@@ -146,7 +147,7 @@ def roundup(x, mod):
 class FPDIVMuxInOut(ReservationStations):
     """ Reservation-Station version of FPDIV pipeline.
 
-        * fan-in on inputs (an array of FPADDBaseData: a,b,mid)
+        * fan-in on inputs (an array of FPBaseData: a,b,mid)
         * N-stage divider pipeline
         * fan-out on outputs (an array of FPPackData: z,mid)
 
@@ -159,15 +160,15 @@ class FPDIVMuxInOut(ReservationStations):
     def __init__(self, width, num_rows, op_wid=2):
         self.id_wid = num_bits(num_rows)
         self.pspec = PipelineSpec(width, self.id_wid, op_wid)
+
         # get the standard mantissa width, store in the pspec
         fmt = FPFormat.standard(width)
         log2_radix = 3     # tested options so far: 1, 2 and 3.
-
         n_comb_stages = 2  # 2 compute stages per pipeline stage
+        maskwid = 1        # SIMD width effectively
 
+        # extra bits needed: guard + round (sticky comes from remainer.bool())
         fraction_width = fmt.fraction_width
-
-        # extra bits needed: guard + round
         fraction_width += 2
 
         # rounding width to a multiple of log2_radix is not needed,
@@ -175,6 +176,8 @@ class FPDIVMuxInOut(ReservationStations):
         # the last stage
         cfg = DivPipeCoreConfig(fmt.width, fraction_width, log2_radix)
 
+        self.pspec.pipekls = MaskCancellableRedir
+        self.pspec.maskwid = maskwid * num_rows # RS gets just maskwid
         self.pspec.fpformat = fmt
         self.pspec.n_comb_stages = n_comb_stages
         self.pspec.core_config = cfg
@@ -185,10 +188,4 @@ class FPDIVMuxInOut(ReservationStations):
         # new_pspec.opkls = DivPipeCoreOperation
         # self.alu = FPDIVBasePipe(new_pspec)
         self.alu = FPDIVBasePipe(self.pspec)
-        ReservationStations.__init__(self, num_rows)
-
-    def i_specfn(self):
-        return FPADDBaseData(self.pspec)
-
-    def o_specfn(self):
-        return FPPackData(self.pspec)
+        ReservationStations.__init__(self, num_rows, maskwid=maskwid)