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[ieee754fpu.git] / src / ieee754 / fpdiv / pipeline.py

diff --git a/src/ieee754/fpdiv/pipeline.py b/src/ieee754/fpdiv/pipeline.py
index 9bfcb49eb1d4e56957475c2dc654b376b834d3d3..6a9cf809d626a7f946fb4a67b2c11bc36280b338 100644 (file)
--- a/src/ieee754/fpdiv/pipeline.py
+++ b/src/ieee754/fpdiv/pipeline.py
@@ -19,7 +19,7 @@ scnorm   - FPDIVSpecialCasesDeNorm ispec FPBaseData
 pipediv0 - FPDivStagesSetup        ispec FPSCData
 --------                           ospec DivPipeInterstageData
 
-                StageChain: FPDivStage0Mod,
+                StageChain: FPDivPreFPAdjust,
                             DivPipeSetupStage,
                             DivPipeCalculateStage,
                             ...
@@ -41,7 +41,7 @@ pipediv5 - FPDivStageFinal         ispec FPDivStage0Data
                             ...
                             DivPipeCalculateStage,
                             DivPipeFinalStage,
-                            FPDivStage2Mod
+                            FPDivPostToFPFormat
 
 normpack - FPNormToPack            ispec FPPostCalcData
 --------                           ospec FPPackData
@@ -177,7 +177,7 @@ class FPDIVMuxInOut(ReservationStations):
         cfg = DivPipeCoreConfig(fmt.width, fraction_width, log2_radix)
 
         self.pspec.pipekls = MaskCancellableRedir
-        self.pspec.maskwid = maskwid
+        self.pspec.maskwid = maskwid * num_rows # RS gets just maskwid
         self.pspec.fpformat = fmt
         self.pspec.n_comb_stages = n_comb_stages
         self.pspec.core_config = cfg