copy context/roundz, a and b manually in fpmul align

[ieee754fpu.git] / src / ieee754 / fpmul / fmul.py

diff --git a/src/ieee754/fpmul/fmul.py b/src/ieee754/fpmul/fmul.py
index 3ad9e53975c7d937d831e9f5f45218474ba47bfa..d775671c7f685a7be8d56c240a55f77096611995 100644 (file)
--- a/src/ieee754/fpmul/fmul.py
+++ b/src/ieee754/fpmul/fmul.py
@@ -1,9 +1,10 @@
 from nmigen import Module, Signal, Cat, Mux, Array, Const
 from nmigen.cli import main, verilog
 
-from ieee754.fpcommon.fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase, FPState
-from fpcommon.getop import FPGetOp
-from nmutil.singlepipe import eq
+from ieee754.fpcommon.fpbase import (FPNumIn, FPNumOut, FPOpIn,
+                                     FPOpOut, Overflow, FPBase, FPState)
+from ieee754.fpcommon.getop import FPGetOp
+from nmutil.nmoperator import eq
 
 
 class FPMUL(FPBase):
@@ -12,9 +13,12 @@ class FPMUL(FPBase):
         FPBase.__init__(self)
         self.width = width
 
-        self.in_a  = FPOp(width)
-        self.in_b  = FPOp(width)
-        self.out_z = FPOp(width)
+        self.in_a  = FPOpIn(width)
+        self.in_a.data_i = Signal(width)
+        self.in_b  = FPOpIn(width)
+        self.in_b.data_i = Signal(width)
+        self.out_z = FPOpOut(width)
+        self.out_z.data_o = Signal(width)
 
         self.states = []
 
@@ -51,14 +55,14 @@ class FPMUL(FPBase):
 
             with m.State("get_a"):
                 res = self.get_op(m, self.in_a, a, "get_b")
-                m.d.sync += eq([a, self.in_a.ack], res)
+                m.d.sync += eq([a, self.in_a.ready_o], res)
 
             # ******
             # gets operand b
 
             with m.State("get_b"):
                 res = self.get_op(m, self.in_b, b, "special_cases")
-                m.d.sync += eq([b, self.in_b.ack], res)
+                m.d.sync += eq([b, self.in_b.ready_o], res)
 
             # ******
             # special cases