code comments

[ieee754fpu.git] / src / ieee754 / fpmul / mul0.py

diff --git a/src/ieee754/fpmul/mul0.py b/src/ieee754/fpmul/mul0.py
index 6b00762a33664eb508c8081b09aff7f5325cac2a..7f19fcfc6d566ae647565e26fccf40139ebfe811 100644 (file)
--- a/src/ieee754/fpmul/mul0.py
+++ b/src/ieee754/fpmul/mul0.py
@@ -41,6 +41,7 @@ class FPMulStage0Mod(PipeModBase):
                      self.o.z.s.eq(self.i.a.s ^ self.i.b.s)
         ]
 
+        # pass through context
         comb += self.o.oz.eq(self.i.oz)
         comb += self.o.out_do_z.eq(self.i.out_do_z)
         comb += self.o.ctx.eq(self.i.ctx)