big (single-purpose) update: move width arg into pspec

[ieee754fpu.git] / src / ieee754 / fpmul / mul0.py

diff --git a/src/ieee754/fpmul/mul0.py b/src/ieee754/fpmul/mul0.py
index db89b33614ab26a1d7199220913500b567d136a7..f56f69b532d524cef9a92a68699c63fcee693563 100644 (file)
--- a/src/ieee754/fpmul/mul0.py
+++ b/src/ieee754/fpmul/mul0.py
@@ -13,13 +13,14 @@ from ieee754.fpcommon.getop import FPPipeContext
 
 class FPMulStage0Data:
 
-    def __init__(self, width, pspec):
+    def __init__(self, pspec):
+        width = pspec['width']
         self.z = FPNumBaseRecord(width, False)
         self.out_do_z = Signal(reset_less=True)
         self.oz = Signal(width, reset_less=True)
         mw = (self.z.m_width)*2 - 1 + 3 # sticky/round/guard bits + (2*mant) - 1
         self.product = Signal(mw, reset_less=True)
-        self.ctx = FPPipeContext(width, pspec)
+        self.ctx = FPPipeContext(pspec)
         self.muxid = self.ctx.muxid
 
     def eq(self, i):
@@ -29,17 +30,16 @@ class FPMulStage0Data:
 
 class FPMulStage0Mod(Elaboratable):
 
-    def __init__(self, width, pspec):
-        self.width = width
+    def __init__(self, pspec):
         self.pspec = pspec
         self.i = self.ispec()
         self.o = self.ospec()
 
     def ispec(self):
-        return FPSCData(self.width, self.pspec, False)
+        return FPSCData(self.pspec, False)
 
     def ospec(self):
-        return FPMulStage0Data(self.width, self.pspec)
+        return FPMulStage0Data(self.pspec)
 
     def process(self, i):
         return self.o