big (single-purpose) update: move width arg into pspec

[ieee754fpu.git] / src / ieee754 / fpmul / mul1.py

diff --git a/src/ieee754/fpmul/mul1.py b/src/ieee754/fpmul/mul1.py
index e6e58fc4da477873ee2a52cb6726ef8b5382fda0..1611fe1835996bd7be3755df6dd22d004a363b2f 100644 (file)
--- a/src/ieee754/fpmul/mul1.py
+++ b/src/ieee754/fpmul/mul1.py
@@ -12,17 +12,16 @@ class FPMulStage1Mod(FPState, Elaboratable):
     """ Second stage of mul: preparation for normalisation.
     """
 
-    def __init__(self, width, pspec):
-        self.width = width
+    def __init__(self, pspec):
         self.pspec = pspec
         self.i = self.ispec()
         self.o = self.ospec()
 
     def ispec(self):
-        return FPMulStage0Data(self.width, self.pspec)
+        return FPMulStage0Data(self.pspec)
 
     def ospec(self):
-        return FPAddStage1Data(self.width, self.pspec)
+        return FPAddStage1Data(self.pspec)
 
     def process(self, i):
         return self.o
@@ -57,9 +56,10 @@ class FPMulStage1Mod(FPState, Elaboratable):
 
 class FPMulStage1(FPState):
 
-    def __init__(self, width, pspec):
+    def __init__(self, pspec):
         FPState.__init__(self, "multiply_1")
-        self.mod = FPMulStage1Mod(width, pspec)
+        width = pspec['width']
+        self.mod = FPMulStage1Mod(pspec)
         self.out_z = FPNumBaseRecord(width, False)
         self.out_of = Overflow()
         self.norm_stb = Signal()