rename FPModBase* to PipeModBase*

[ieee754fpu.git] / src / ieee754 / fpmul / mul1.py

diff --git a/src/ieee754/fpmul/mul1.py b/src/ieee754/fpmul/mul1.py
index 9f896315d2e97e324e0e6e93bd71d4f2515d70e7..67e915172d9427e2135315bf6aed3e8e26cbd1fb 100644 (file)
--- a/src/ieee754/fpmul/mul1.py
+++ b/src/ieee754/fpmul/mul1.py
@@ -7,12 +7,12 @@ Copyright (C) 2019 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 from nmigen import Module, Signal, Elaboratable
 from nmigen.cli import main, verilog
 
-from nmutil.pipemodbase import FPModBase
+from nmutil.pipemodbase import PipeModBase
 from ieee754.fpcommon.postcalc import FPAddStage1Data
 from ieee754.fpmul.mul0 import FPMulStage0Data
 
 
-class FPMulStage1Mod(FPModBase):
+class FPMulStage1Mod(PipeModBase):
     """ Second stage of mul: preparation for normalisation.
     """