fix multiply bit-width

[ieee754fpu.git] / src / ieee754 / fpmul / mulstages.py

diff --git a/src/ieee754/fpmul/mulstages.py b/src/ieee754/fpmul/mulstages.py
index adf68d38dbef52bb505806a1102174f496071157..e07b05aab1fe0c025688c05b397891d43cafa682 100644 (file)
--- a/src/ieee754/fpmul/mulstages.py
+++ b/src/ieee754/fpmul/mulstages.py
@@ -22,7 +22,7 @@ class FPMulStages(FPState, SimpleHandshake):
         self.m1o = self.ospec()
 
     def ispec(self):
-        return FPSCData(self.width, self.id_wid)
+        return FPSCData(self.width, self.id_wid, False)
 
     def ospec(self):
         return FPAddStage1Data(self.width, self.id_wid) # AddStage1 ospec