copy context/roundz, a and b manually in fpmul align

[ieee754fpu.git] / src / ieee754 / fpmul / pipeline.py

diff --git a/src/ieee754/fpmul/pipeline.py b/src/ieee754/fpmul/pipeline.py
index 0f49a37dd139cbad9d1f4b5e3918f3e5201fbfe0..08c151d0020105864724dc8d1505e45c4954480c 100644 (file)
--- a/src/ieee754/fpmul/pipeline.py
+++ b/src/ieee754/fpmul/pipeline.py
@@ -5,9 +5,7 @@
 from nmigen import Module
 from nmigen.cli import main, verilog
 
-from nmutil.singlepipe import (ControlBase, SimpleHandshake, PassThroughStage)
-from nmutil.multipipe import CombMuxOutPipe
-from nmutil.multipipe import PriorityCombMuxInPipe
+from nmutil.singlepipe import ControlBase
 from nmutil.concurrentunit import ReservationStations, num_bits
 
 from ieee754.fpcommon.getop import FPADDBaseData
@@ -15,16 +13,16 @@ from ieee754.fpcommon.denorm import FPSCData
 from ieee754.fpcommon.pack import FPPackData
 from ieee754.fpcommon.normtopack import FPNormToPack
 from .specialcases import FPMulSpecialCasesDeNorm
-from .addstages import FPMulStages
-
+from .mulstages import FPMulStages
+from ieee754.pipeline import PipelineSpec
 
 
 class FPMULBasePipe(ControlBase):
-    def __init__(self, width, id_wid):
+    def __init__(self, pspec):
         ControlBase.__init__(self)
-        self.pipe1 = FPMulSpecialCasesDeNorm(width, id_wid)
-        self.pipe2 = FPMulStages(width, id_wid)
-        self.pipe3 = FPNormToPack(width, id_wid)
+        self.pipe1 = FPMulSpecialCasesDeNorm(pspec)
+        self.pipe2 = FPMulStages(pspec)
+        self.pipe3 = FPNormToPack(pspec)
 
         self._eqs = self.connect([self.pipe1, self.pipe2, self.pipe3])
 
@@ -41,19 +39,21 @@ class FPMULMuxInOut(ReservationStations):
     """ Reservation-Station version of FPMUL pipeline.
 
         * fan-in on inputs (an array of FPADDBaseData: a,b,mid)
-        * 3-stage adder pipeline
+        * 2-stage multiplier pipeline
         * fan-out on outputs (an array of FPPackData: z,mid)
 
         Fan-in and Fan-out are combinatorial.
     """
-    def __init__(self, width, num_rows):
-        self.width = width
+
+    def __init__(self, width, num_rows, op_wid=0):
         self.id_wid = num_bits(width)
-        self.alu = FPMULBasePipe(width, self.id_wid)
+        self.op_wid = op_wid
+        self.pspec = PipelineSpec(width, self.id_wid, self.op_wid)
+        self.alu = FPMULBasePipe(self.pspec)
         ReservationStations.__init__(self, num_rows)
 
     def i_specfn(self):
-        return FPADDBaseData(self.width, self.id_wid)
+        return FPADDBaseData(self.pspec)
 
     def o_specfn(self):
-        return FPPackData(self.width, self.id_wid)
+        return FPPackData(self.pspec)