copy context/roundz, a and b manually in fpmul align

[ieee754fpu.git] / src / ieee754 / fpmul / pipeline.py

diff --git a/src/ieee754/fpmul/pipeline.py b/src/ieee754/fpmul/pipeline.py
index f146b1a70bd67c6bf5b34d93a2e883d3c3b5b559..08c151d0020105864724dc8d1505e45c4954480c 100644 (file)
--- a/src/ieee754/fpmul/pipeline.py
+++ b/src/ieee754/fpmul/pipeline.py
@@ -14,7 +14,7 @@ from ieee754.fpcommon.pack import FPPackData
 from ieee754.fpcommon.normtopack import FPNormToPack
 from .specialcases import FPMulSpecialCasesDeNorm
 from .mulstages import FPMulStages
-
+from ieee754.pipeline import PipelineSpec
 
 
 class FPMULBasePipe(ControlBase):
@@ -44,13 +44,11 @@ class FPMULMuxInOut(ReservationStations):
 
         Fan-in and Fan-out are combinatorial.
     """
+
     def __init__(self, width, num_rows, op_wid=0):
-        self.pspec = {}
         self.id_wid = num_bits(width)
         self.op_wid = op_wid
-        self.pspec['id_wid'] = self.id_wid
-        self.pspec['width'] = width
-        self.pspec['op_wid'] = self.op_wid
+        self.pspec = PipelineSpec(width, self.id_wid, self.op_wid)
         self.alu = FPMULBasePipe(self.pspec)
         ReservationStations.__init__(self, num_rows)