copy context/roundz, a and b manually in fpmul align

[ieee754fpu.git] / src / ieee754 / fpmul / specialcases.py

diff --git a/src/ieee754/fpmul/specialcases.py b/src/ieee754/fpmul/specialcases.py
index 83f82558b9e6c8015bd4f83c1b15811d5b0819fe..8e0fada2824094a29a1a320275e6ee6820b448f8 100644 (file)
--- a/src/ieee754/fpmul/specialcases.py
+++ b/src/ieee754/fpmul/specialcases.py
@@ -4,12 +4,13 @@ from nmigen import Module, Signal, Cat, Const, Elaboratable
 from nmigen.cli import main, verilog
 from math import log
 
-from ieee754.fpcommon.fpbase import FPNumDecode
+from ieee754.fpcommon.fpbase import FPNumDecode, FPNumBaseRecord
 from nmutil.singlepipe import SimpleHandshake, StageChain
 
 from ieee754.fpcommon.fpbase import FPState, FPID
 from ieee754.fpcommon.getop import FPADDBaseData
 from ieee754.fpcommon.denorm import (FPSCData, FPAddDeNormMod)
+from ieee754.fpmul.align import FPAlignModSingle
 
 
 class FPMulSpecialCasesMod(Elaboratable):
@@ -18,17 +19,16 @@ class FPMulSpecialCasesMod(Elaboratable):
         https://steve.hollasch.net/cgindex/coding/ieeefloat.html
     """
 
-    def __init__(self, width, id_wid):
-        self.width = width
-        self.id_wid = id_wid
+    def __init__(self, pspec):
+        self.pspec = pspec
         self.i = self.ispec()
         self.o = self.ospec()
 
     def ispec(self):
-        return FPADDBaseData(self.width, self.id_wid)
+        return FPADDBaseData(self.pspec)
 
     def ospec(self):
-        return FPSCData(self.width, self.id_wid, False)
+        return FPSCData(self.pspec, False)
 
     def setup(self, m, i):
         """ links module to inputs and outputs
@@ -42,13 +42,14 @@ class FPMulSpecialCasesMod(Elaboratable):
     def elaborate(self, platform):
         m = Module()
 
-        m.submodules.sc_out_z = self.o.z
+        #m.submodules.sc_out_z = self.o.z
 
         # decode: XXX really should move to separate stage
-        a1 = FPNumDecode(None, self.width, False)
-        b1 = FPNumDecode(None, self.width, False)
-        m.submodules.sc_decode_a = a1
-        m.submodules.sc_decode_b = b1
+        width = self.pspec.width
+        a1 = FPNumBaseRecord(width, False)
+        b1 = FPNumBaseRecord(width, False)
+        m.submodules.sc_decode_a = a1 = FPNumDecode(None, a1)
+        m.submodules.sc_decode_b = b1 = FPNumDecode(None, b1)
         m.d.comb += [a1.v.eq(self.i.a),
                      b1.v.eq(self.i.b),
                      self.o.a.eq(a1),
@@ -67,7 +68,7 @@ class FPMulSpecialCasesMod(Elaboratable):
         # if a is NaN or b is NaN return NaN
         with m.If(abnan):
             m.d.comb += self.o.out_do_z.eq(1)
-            m.d.comb += self.o.z.nan(1)
+            m.d.comb += self.o.z.nan(0)
 
         # if a is inf return inf (or NaN)
         with m.Elif(a1.is_inf):
@@ -75,7 +76,7 @@ class FPMulSpecialCasesMod(Elaboratable):
             m.d.comb += self.o.z.inf(sabx)
             # b is zero return NaN
             with m.If(b1.is_zero):
-                m.d.comb += self.o.z.nan(1)
+                m.d.comb += self.o.z.nan(0)
 
         # if b is inf return inf (or NaN)
         with m.Elif(b1.is_inf):
@@ -83,7 +84,7 @@ class FPMulSpecialCasesMod(Elaboratable):
             m.d.comb += self.o.z.inf(sabx)
             # a is zero return NaN
             with m.If(a1.is_zero):
-                m.d.comb += self.o.z.nan(1)
+                m.d.comb += self.o.z.nan(0)
 
         # if a is zero or b zero return signed-a/b
         with m.Elif(obz):
@@ -95,7 +96,7 @@ class FPMulSpecialCasesMod(Elaboratable):
             m.d.comb += self.o.out_do_z.eq(0)
 
         m.d.comb += self.o.oz.eq(self.o.z.v)
-        m.d.comb += self.o.mid.eq(self.i.mid)
+        m.d.comb += self.o.ctx.eq(self.i.ctx)
 
         return m
 
@@ -117,7 +118,7 @@ class FPMulSpecialCases(FPState):
         """
         self.mod.setup(m, i, self.out_do_z)
         m.d.sync += self.out_z.v.eq(self.mod.out_z.v) # only take the output
-        m.d.sync += self.out_z.mid.eq(self.mod.o.mid)  # (and mid)
+        m.d.sync += self.out_z.ctx.eq(self.mod.o.ctx)  # (and context)
 
     def action(self, m):
         self.idsync(m)
@@ -131,32 +132,32 @@ class FPMulSpecialCasesDeNorm(FPState, SimpleHandshake):
     """ special cases: NaNs, infs, zeros, denormalised
     """
 
-    def __init__(self, width, id_wid):
+    def __init__(self, pspec):
         FPState.__init__(self, "special_cases")
-        self.width = width
-        self.id_wid = id_wid
+        self.pspec = pspec
         SimpleHandshake.__init__(self, self) # pipe is its own stage
         self.out = self.ospec()
 
     def ispec(self):
-        return FPADDBaseData(self.width, self.id_wid) # SpecialCases ispec
+        return FPADDBaseData(self.pspec)
 
     def ospec(self):
-        return FPSCData(self.width, self.id_wid, False) # DeNorm ospec
+        return FPSCData(self.pspec, False)
 
     def setup(self, m, i):
         """ links module to inputs and outputs
         """
-        smod = FPMulSpecialCasesMod(self.width, self.id_wid)
-        dmod = FPAddDeNormMod(self.width, self.id_wid, False)
+        smod = FPMulSpecialCasesMod(self.pspec)
+        dmod = FPAddDeNormMod(self.pspec, False)
+        amod = FPAlignModSingle(self.pspec, False)
 
-        chain = StageChain([smod, dmod])
+        chain = StageChain([smod, dmod, amod])
         chain.setup(m, i)
 
         # only needed for break-out (early-out)
         # self.out_do_z = smod.o.out_do_z
 
-        self.o = dmod.o
+        self.o = amod.o # output is from last .o in the chain
 
     def process(self, i):
         return self.o