get fp mul pipe working using new FPNumBaseRecord

[ieee754fpu.git] / src / ieee754 / fpmul / specialcases.py

diff --git a/src/ieee754/fpmul/specialcases.py b/src/ieee754/fpmul/specialcases.py
index 83f82558b9e6c8015bd4f83c1b15811d5b0819fe..b7a59b37950a5425497db1a2b5e4d8457265b7ab 100644 (file)
--- a/src/ieee754/fpmul/specialcases.py
+++ b/src/ieee754/fpmul/specialcases.py
@@ -4,7 +4,7 @@ from nmigen import Module, Signal, Cat, Const, Elaboratable
 from nmigen.cli import main, verilog
 from math import log
 
-from ieee754.fpcommon.fpbase import FPNumDecode
+from ieee754.fpcommon.fpbase import FPNumDecode, FPNumBaseRecord
 from nmutil.singlepipe import SimpleHandshake, StageChain
 
 from ieee754.fpcommon.fpbase import FPState, FPID
@@ -42,13 +42,13 @@ class FPMulSpecialCasesMod(Elaboratable):
     def elaborate(self, platform):
         m = Module()
 
-        m.submodules.sc_out_z = self.o.z
+        #m.submodules.sc_out_z = self.o.z
 
         # decode: XXX really should move to separate stage
-        a1 = FPNumDecode(None, self.width, False)
-        b1 = FPNumDecode(None, self.width, False)
-        m.submodules.sc_decode_a = a1
-        m.submodules.sc_decode_b = b1
+        a1 = FPNumBaseRecord(self.width, False)
+        b1 = FPNumBaseRecord(self.width, False)
+        m.submodules.sc_decode_a = a1 = FPNumDecode(None, a1)
+        m.submodules.sc_decode_b = b1 = FPNumDecode(None, b1)
         m.d.comb += [a1.v.eq(self.i.a),
                      b1.v.eq(self.i.b),
                      self.o.a.eq(a1),