format code

[ieee754fpu.git] / src / ieee754 / fpmul / test / test_fpmul_pipe_32.py

diff --git a/src/ieee754/fpmul/test/test_fpmul_pipe_32.py b/src/ieee754/fpmul/test/test_fpmul_pipe_32.py
index cebf97ff143a242a467fda7c4978cad50834b774..058ce307b6f2e427a00c46e2440647c2a0ef53dd 100644 (file)
--- a/src/ieee754/fpmul/test/test_fpmul_pipe_32.py
+++ b/src/ieee754/fpmul/test/test_fpmul_pipe_32.py
@@ -1,7 +1,7 @@
 """ test of FPMULMuxInOut
 """
 
-from ieee754.fpmul.pipeline import (FPMULMuxInOut,)
+from ieee754.fpmul.pipeline import FPMULMuxInOut
 from ieee754.fpcommon.test.case_gen import run_pipe_fp
 from ieee754.fpcommon.test import unit_test_single
 from ieee754.fpmul.test.mul_data32 import regressions
@@ -13,7 +13,7 @@ from operator import mul
 def test_pipe_fp32():
     dut = FPMULMuxInOut(32, 4)
     run_pipe_fp(dut, 32, "mul", unit_test_single, Float32,
-                   regressions, mul, 10)
+                regressions, mul, 10)
 
 
 if __name__ == '__main__':