"""
Copyright (C) 2020 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Copyright (C) 2020 Michael Nolan <mtnolan2640@gmail.com>
dynamically-partitionable "comparison" class, directly equivalent
-to Signal.__eq__ except SIMD-partitionable
+to Signal.__eq__, __gt__ and __ge__, except SIMD-partitionable
See:
-* http://libre-riscv.org/3d_gpu/architecture/dynamic_simd/eq
+* http://libre-riscv.org/3d_gpu/architecture/dynamic_simd/
* http://bugs.libre-riscv.org/show_bug.cgi?id=132
+* http://bugs.libre-riscv.org/show_bug.cgi?id=171
"""
-from nmigen import Signal, Module, Elaboratable, Cat, C, Mux, Repl
-from nmigen.back.pysim import Simulator, Delay, Settle
-from nmigen.cli import main, rtlil
+from nmigen import Signal, Module, Elaboratable, Cat, C
+from nmigen.back.pysim import Simulator, Delay
from ieee754.part_mul_add.partpoints import PartitionPoints
from ieee754.part_cmp.gt_combiner import GTCombiner
self.partition_points = PartitionPoints(partition_points)
self.mwidth = len(self.partition_points)+1
self.output = Signal(self.mwidth, reset_less=True)
- if not self.partition_points.fits_in_width(width):
- raise ValueError("partition_points doesn't fit in width")
+ assert self.partition_points.fits_in_width(width), \
+ "partition_points doesn't fit in width"
def elaborate(self, platform):
m = Module()
self.partition_points.as_sig(),
self.output]
+
if __name__ == "__main__":
from ieee754.part_mul_add.partpoints import make_partition
m = Module()