add bit of extra explanatory comment for carry-ripple thing

[ieee754fpu.git] / src / ieee754 / part_mul_add / adder.py

diff --git a/src/ieee754/part_mul_add/adder.py b/src/ieee754/part_mul_add/adder.py
index 2eb6de27e868b8f1f3be78604400361a70561760..1ade9f840f5d407e6203aeb023e13d18018bea50 100644 (file)
--- a/src/ieee754/part_mul_add/adder.py
+++ b/src/ieee754/part_mul_add/adder.py
@@ -261,6 +261,11 @@ class PartitionedAdder(Elaboratable):
         # special hardware on FPGAs
         comb += expanded_o.eq(expanded_a + expanded_b)
 
+        # ok now we have the carry-out, however because it's the MSB it's
+        # in the wrong position in the output as far as putting it into
+        # a chain of adds (or other operations).  therefore we need to
+        # "ripple" carry-out down to the same position that carry-in is
+        # in [the LSB of each partition].
         comb += ripple.results_in.eq(carry_tmp)
         comb += ripple.gates.eq(self.part_pts.as_sig())
         comb += self.carry_out.eq(ripple.output)