FULL_ADDER_INPUT_COUNT = 3
+class AddReduceData:
+
+ def __init__(self, ppoints, output_width, n_parts):
+ self.part_ops = [Signal(2, name=f"part_ops_{i}")
+ for i in range(n_parts)]
+ self.inputs = [Signal(output_width, name=f"inputs[{i}]")
+ for i in range(len(self.inputs))]
+ self.reg_partition_points = partition_points.like()
+
+ def eq(self, rhs):
+ return [self.reg_partition_points.eq(rhs.reg_partition_points)] + \
+ [self.inputs[i].eq(rhs.inputs[i])
+ for i in range(len(self.inputs))] + \
+ [self.part_ops[i].eq(rhs.part_ops[i])
+ for i in range(len(self.part_ops))]
+
+
+class FinalAdd(Elaboratable):
+ """ Final stage of add reduce
+ """
+
+ def __init__(self, inputs, output_width, register_levels, partition_points,
+ part_ops):
+ self.part_ops = part_ops
+ self.out_part_ops = [Signal(2, name=f"out_part_ops_{i}")
+ for i in range(len(part_ops))]
+ self.inputs = list(inputs)
+ self._resized_inputs = [
+ Signal(output_width, name=f"resized_inputs[{i}]")
+ for i in range(len(self.inputs))]
+ self.register_levels = list(register_levels)
+ self.output = Signal(output_width)
+ self.partition_points = PartitionPoints(partition_points)
+ if not self.partition_points.fits_in_width(output_width):
+ raise ValueError("partition_points doesn't fit in output_width")
+ self._reg_partition_points = self.partition_points.like()
+
+ def elaborate(self, platform):
+ """Elaborate this module."""
+ m = Module()
+
+ if len(self.inputs) == 0:
+ # use 0 as the default output value
+ m.d.comb += self.output.eq(0)
+ elif len(self.inputs) == 1:
+ # handle single input
+ m.d.comb += self.output.eq(self._resized_inputs[0])
+ else:
+ # base case for adding 2 inputs
+ assert len(self.inputs) == 2
+ adder = PartitionedAdder(len(self.output),
+ self._reg_partition_points)
+ m.submodules.final_adder = adder
+ m.d.comb += adder.a.eq(self._resized_inputs[0])
+ m.d.comb += adder.b.eq(self._resized_inputs[1])
+ m.d.comb += self.output.eq(adder.output)
+ return m
+
class AddReduceSingle(Elaboratable):
"""Add list of numbers together.
pipeline registers.
:param partition_points: the input partition points.
"""
+ self.output_width = output_width
self.part_ops = part_ops
self.out_part_ops = [Signal(2, name=f"out_part_ops_{i}")
for i in range(len(part_ops))]
Signal(output_width, name=f"resized_inputs[{i}]")
for i in range(len(self.inputs))]
self.register_levels = list(register_levels)
- self.output = Signal(output_width)
self.partition_points = PartitionPoints(partition_points)
if not self.partition_points.fits_in_width(output_width):
raise ValueError("partition_points doesn't fit in output_width")
"""Elaborate this module."""
m = Module()
- # resize inputs to correct bit-width and optionally add in
- # pipeline registers
- resized_input_assignments = [self._resized_inputs[i].eq(self.inputs[i])
- for i in range(len(self.inputs))]
- copy_part_ops = [self.out_part_ops[i].eq(self.part_ops[i])
- for i in range(len(self.part_ops))]
- if 0 in self.register_levels:
- m.d.sync += copy_part_ops
- m.d.sync += resized_input_assignments
- m.d.sync += self._reg_partition_points.eq(self.partition_points)
- else:
- m.d.comb += copy_part_ops
- m.d.comb += resized_input_assignments
- m.d.comb += self._reg_partition_points.eq(self.partition_points)
-
for (value, term) in self._intermediate_terms:
m.d.comb += term.eq(value)
- # if there are no full adders to create, then we handle the base cases
- # and return, otherwise we go on to the recursive case
- if len(self.groups) == 0:
- if len(self.inputs) == 0:
- # use 0 as the default output value
- m.d.comb += self.output.eq(0)
- elif len(self.inputs) == 1:
- # handle single input
- m.d.comb += self.output.eq(self._resized_inputs[0])
- else:
- # base case for adding 2 inputs
- assert len(self.inputs) == 2
- adder = PartitionedAdder(len(self.output),
- self._reg_partition_points)
- m.submodules.final_adder = adder
- m.d.comb += adder.a.eq(self._resized_inputs[0])
- m.d.comb += adder.b.eq(self._resized_inputs[1])
- m.d.comb += self.output.eq(adder.output)
- return m
-
- mask = self._reg_partition_points.as_mask(len(self.output))
+ mask = self._reg_partition_points.as_mask(self.output_width)
m.d.comb += self.part_mask.eq(mask)
# add and link the intermediate term modules
def add_intermediate_term(value):
intermediate_term = Signal(
- len(self.output),
+ self.output_width,
name=f"intermediate_terms[{len(intermediate_terms)}]")
_intermediate_terms.append((value, intermediate_term))
intermediate_terms.append(intermediate_term)
# store mask in intermediary (simplifies graph)
- self.part_mask = Signal(len(self.output), reset_less=True)
+ self.part_mask = Signal(self.output_width, reset_less=True)
# create full adders for this recursive level.
# this shrinks N terms to 2 * (N // 3) plus the remainder
self.adders = []
for i in self.groups:
- adder_i = MaskedFullAdder(len(self.output))
+ adder_i = MaskedFullAdder(self.output_width)
self.adders.append((i, adder_i))
# add both the sum and the masked-carry to the next level.
# 3 inputs have now been reduced to 2...
next_level = AddReduceSingle(inputs, self.output_width, next_levels,
partition_points, part_ops)
mods.append(next_level)
- if len(next_level.groups) == 0:
- break
next_levels = list(AddReduce.next_register_levels(next_levels))
partition_points = next_level._reg_partition_points
inputs = next_level.intermediate_terms
part_ops = next_level.out_part_ops
+ groups = AddReduceSingle.full_adder_groups(len(inputs))
+ if len(groups) == 0:
+ break
+
+ next_level = FinalAdd(inputs, self.output_width, next_levels,
+ partition_points, part_ops)
+ mods.append(next_level)
self.levels = mods
for i, next_level in enumerate(self.levels):
setattr(m.submodules, "next_level%d" % i, next_level)
+ for i in range(len(self.levels)):
+ mcur = self.levels[i]
+ #mnext = self.levels[i+1]
+ inassign = [mcur._resized_inputs[i].eq(mcur.inputs[i])
+ for i in range(len(mcur.inputs))]
+ copy_part_ops = [mcur.out_part_ops[i].eq(mcur.part_ops[i])
+ for i in range(len(mcur.part_ops))]
+ if 0 in mcur.register_levels:
+ m.d.sync += copy_part_ops
+ m.d.sync += inassign
+ m.d.sync += mcur._reg_partition_points.eq(mcur.partition_points)
+ else:
+ m.d.comb += copy_part_ops
+ m.d.comb += inassign
+ m.d.comb += mcur._reg_partition_points.eq(mcur.partition_points)
+
# output comes from last module
m.d.comb += self.output.eq(next_level.output)
copy_part_ops = [self.out_part_ops[i].eq(next_level.out_part_ops[i])
# outputs
self.parts = [Signal(name=f"part_{i}") for i in range(n_parts)]
- self.delayed_parts = [
- [Signal(name=f"delayed_part_{delay}_{i}")
- for i in range(n_parts)]
- for delay in range(n_levels)]
- # XXX REALLY WEIRD BUG - have to take a copy of the last delayed_parts
- self.dplast = [Signal(name=f"dplast_{i}")
- for i in range(n_parts)]
self.not_a_term = Signal(width)
self.neg_lsb_a_term = Signal(width)
def elaborate(self, platform):
m = Module()
- pbs, parts, delayed_parts = self.pbs, self.parts, self.delayed_parts
+ pbs, parts = self.pbs, self.parts
epps = self.epps
m.submodules.p = p = Parts(self.pbwid, epps, len(parts))
m.d.comb += p.epps.eq(epps)
parts = p.parts
- npbs = Signal.like(pbs, reset_less=True)
byte_count = 8 // len(parts)
- for i in range(len(parts)):
- m.d.comb += delayed_parts[0][i].eq(parts[i])
- m.d.sync += [delayed_parts[j + 1][i].eq(delayed_parts[j][i])
- for j in range(len(delayed_parts)-1)]
- m.d.comb += self.dplast[i].eq(delayed_parts[-1][i])
- not_a_term, neg_lsb_a_term, not_b_term, neg_lsb_b_term = \
- self.not_a_term, self.neg_lsb_a_term, \
- self.not_b_term, self.neg_lsb_b_term
+ not_a_term, neg_lsb_a_term, not_b_term, neg_lsb_b_term = (
+ self.not_a_term, self.neg_lsb_a_term,
+ self.not_b_term, self.neg_lsb_b_term)
byte_width = 8 // len(parts) # byte width
bit_wid = 8 * byte_width # bit width
self.part_ops)
out_part_ops = add_reduce.levels[-1].out_part_ops
+ out_part_pts = add_reduce.levels[-1]._reg_partition_points
m.submodules.add_reduce = add_reduce
m.d.comb += self._intermediate_output.eq(add_reduce.output)
for i in range(8):
m.d.comb += io8.part_ops[i].eq(out_part_ops[i])
+ m.submodules.p_8 = p_8 = Parts(8, eps, len(part_8.parts))
+ m.submodules.p_16 = p_16 = Parts(8, eps, len(part_16.parts))
+ m.submodules.p_32 = p_32 = Parts(8, eps, len(part_32.parts))
+ m.submodules.p_64 = p_64 = Parts(8, eps, len(part_64.parts))
+
+ m.d.comb += p_8.epps.eq(out_part_pts)
+ m.d.comb += p_16.epps.eq(out_part_pts)
+ m.d.comb += p_32.epps.eq(out_part_pts)
+ m.d.comb += p_64.epps.eq(out_part_pts)
+
# final output
m.submodules.finalout = finalout = FinalOut(64)
- for i in range(len(part_8.delayed_parts[-1])):
- m.d.comb += finalout.d8[i].eq(part_8.dplast[i])
- for i in range(len(part_16.delayed_parts[-1])):
- m.d.comb += finalout.d16[i].eq(part_16.dplast[i])
- for i in range(len(part_32.delayed_parts[-1])):
- m.d.comb += finalout.d32[i].eq(part_32.dplast[i])
+ for i in range(len(part_8.parts)):
+ m.d.comb += finalout.d8[i].eq(p_8.parts[i])
+ for i in range(len(part_16.parts)):
+ m.d.comb += finalout.d16[i].eq(p_16.parts[i])
+ for i in range(len(part_32.parts)):
+ m.d.comb += finalout.d32[i].eq(p_32.parts[i])
m.d.comb += finalout.i8.eq(io8.output)
m.d.comb += finalout.i16.eq(io16.output)
m.d.comb += finalout.i32.eq(io32.output)