generate ilang for each part mul test

[ieee754fpu.git] / src / ieee754 / part_mul_add / test / test_multiply.py

diff --git a/src/ieee754/part_mul_add/test/test_multiply.py b/src/ieee754/part_mul_add/test/test_multiply.py
index d96d45c138d97e8f88edc39bb4e49d202f7bb8dd..409d482f0edee991f539f5d9f18bac57ee5ad9c7 100644 (file)
--- a/src/ieee754/part_mul_add/test/test_multiply.py
+++ b/src/ieee754/part_mul_add/test/test_multiply.py
@@ -14,11 +14,19 @@ import unittest
 from hashlib import sha256
 import enum
 import pdb
+from nmigen.cli import verilog, rtlil
+
+
+def create_ilang(dut, traces, test_name):
+    vl = rtlil.convert(dut, ports=traces)
+    with open("%s.il" % test_name, "w") as f:
+        f.write(vl)
 
 
 def create_simulator(module: Any,
                      traces: List[Signal],
                      test_name: str) -> Simulator:
+    create_ilang(module, traces, test_name)
     return Simulator(module,
                      vcd_file=open(test_name + ".vcd", "w"),
                      gtkw_file=open(test_name + ".gtkw", "w"),
@@ -153,7 +161,7 @@ class TestAddReduce(unittest.TestCase):
             for value in values:
                 v += value & mask
             y |= mask & v
-        output = (yield module.output)
+        output = (yield module.o.output)
         if gen_or_check == GenOrCheck.Check:
             self.assertEqual(y, output, f"0x{y:X} != 0x{output:X}")
         yield Tick()
@@ -250,17 +258,15 @@ class TestAddReduce(unittest.TestCase):
         module = AddReduce(inputs,
                            width,
                            register_levels,
-                           partition_points)
+                           partition_points,
+                           [])
         file_name = "add_reduce"
         if len(register_levels) != 0:
             file_name += f"-{'_'.join(map(repr, register_levels))}"
         file_name += f"-{input_count:02d}"
-        with create_simulator(module,
-                              [partition_4,
-                               partition_8,
-                               *inputs,
-                               module.output],
-                              file_name) as sim:
+        ports = [partition_4, partition_8, *inputs, module.o.output]
+        #create_ilang(module, ports, file_name)
+        with create_simulator(module, ports, file_name) as sim:
             self.subtest_run_sim(input_count,
                                  sim,
                                  partition_4,
@@ -455,7 +461,7 @@ class TestMul8_16_32_64(unittest.TestCase):
         output2, intermediate_output2 = self.simd_mul(a, b, lanes)
         yield Delay(1e-6)
         if gen_or_check == GenOrCheck.Check:
-            intermediate_output = (yield module._intermediate_output)
+            intermediate_output = (yield module.intermediate_output)
             self.assertEqual(intermediate_output,
                              intermediate_output2,
                              f"0x{intermediate_output:X} "
@@ -521,18 +527,10 @@ class TestMul8_16_32_64(unittest.TestCase):
             file_name += f"-{'_'.join(map(repr, register_levels))}"
         ports = [module.a,
                  module.b,
-                 module._intermediate_output,
+                 module.intermediate_output,
                  module.output]
         ports.extend(module.part_ops)
         ports.extend(module.part_pts.values())
-        for signals in module._delayed_part_ops:
-            ports.extend(signals)
-        ports += [module._output_64,
-                  module._output_32,
-                  module._output_16,
-                  module._output_8]
-        ports.extend(module._a_signed)
-        ports.extend(module._b_signed)
         with create_simulator(module, ports, file_name) as sim:
             def process(gen_or_check: GenOrCheck) -> AsyncProcessGenerator:
                 for a_signed in False, True: