deal with zero-width ShiftMask

[ieee754fpu.git] / src / ieee754 / part_shift / part_shift_dynamic.py

diff --git a/src/ieee754/part_shift/part_shift_dynamic.py b/src/ieee754/part_shift/part_shift_dynamic.py
index 45ba08ca66f2b76a675c4fee606494d0b0a8cbc7..c051397bd52b0e7d8595efdb80c1c92a546cafbb 100644 (file)
--- a/src/ieee754/part_shift/part_shift_dynamic.py
+++ b/src/ieee754/part_shift/part_shift_dynamic.py
@@ -29,6 +29,11 @@ class ShifterMask(Elaboratable):
         m = Module()
         comb = m.d.comb
 
+        # zero-width mustn't try to do anything
+        if self.pwid == 0:
+            self.mask.eq((1<<min_bits)-1)
+            return m
+
         bits = Signal(self.pwid, reset_less=True)
         bl = []
         for j in range(self.pwid):