package sifive.blocks.devices.gpio
import Chisel._
-import config._
-import regmapper._
-import uncore.tilelink2._
-import rocketchip.PeripheryBusConfig
-import util.AsyncResetRegVec
-
-case class GPIOConfig(address: BigInt, width: Int)
-
-trait HasGPIOParameters {
- val params: Tuple2[Parameters, GPIOConfig]
- implicit val p = params._1
- val c = params._2
-}
+import freechips.rocketchip.config.Parameters
+import freechips.rocketchip.regmapper._
+import freechips.rocketchip.tilelink._
+import freechips.rocketchip.util.{AsyncResetRegVec, GenericParameterizedBundle}
+
+case class GPIOParams(address: BigInt, width: Int, includeIOF: Boolean = false)
// YAGNI: Make the PUE, DS, and
// these also optionally HW controllable.
// level, and we have to do the pinmux
// outside of RocketChipTop.
-class GPIOPortIO(c: GPIOConfig) extends Bundle {
+class GPIOPortIO(c: GPIOParams) extends GenericParameterizedBundle(c) {
val pins = Vec(c.width, new GPIOPin)
- val iof_0 = Vec(c.width, new GPIOPinIOF).flip
- val iof_1 = Vec(c.width, new GPIOPinIOF).flip
+ val iof_0 = if (c.includeIOF) Some(Vec(c.width, new GPIOPinIOF).flip) else None
+ val iof_1 = if (c.includeIOF) Some(Vec(c.width, new GPIOPinIOF).flip) else None
}
// It would be better if the IOF were here and
// we could do the pinmux inside.
-trait GPIOBundle extends Bundle with HasGPIOParameters {
- val port = new GPIOPortIO(c)
+trait HasGPIOBundleContents extends Bundle {
+ val params: GPIOParams
+ val port = new GPIOPortIO(params)
}
-trait GPIOModule extends Module with HasGPIOParameters with HasRegMap {
- val io: GPIOBundle
+trait HasGPIOModuleContents extends Module with HasRegMap {
+ val io: HasGPIOBundleContents
+ val params: GPIOParams
+ val c = params
//--------------------------------------------------
// CSR Declarations
// HW IO Function
val iofEnReg = Module(new AsyncResetRegVec(c.width, 0))
val iofSelReg = Reg(init = UInt(0, c.width))
-
+
// Invert Output
val xorReg = Reg(init = UInt(0, c.width))
val rise = ~valueReg & inSyncReg;
val fall = valueReg & ~inSyncReg;
+ val iofEnFields = if (c.includeIOF) (Seq(RegField.rwReg(c.width, iofEnReg.io))) else (Seq(RegField(c.width)))
+ val iofSelFields = if (c.includeIOF) (Seq(RegField(c.width, iofSelReg))) else (Seq(RegField(c.width)))
+
+
// Note that these are out of order.
regmap(
GPIOCtrlRegs.value -> Seq(RegField.r(c.width, valueReg)),
GPIOCtrlRegs.low_ip -> Seq(RegField.w1ToClear(c.width,lowIpReg, ~valueReg)),
GPIOCtrlRegs.port -> Seq(RegField(c.width, portReg)),
GPIOCtrlRegs.pullup_en -> Seq(RegField.rwReg(c.width, pueReg.io)),
- GPIOCtrlRegs.iof_en -> Seq(RegField.rwReg(c.width, iofEnReg.io)),
- GPIOCtrlRegs.iof_sel -> Seq(RegField(c.width, iofSelReg)),
+ GPIOCtrlRegs.iof_en -> iofEnFields,
+ GPIOCtrlRegs.iof_sel -> iofSelFields,
GPIOCtrlRegs.drive -> Seq(RegField(c.width, dsReg)),
GPIOCtrlRegs.input_en -> Seq(RegField.rwReg(c.width, ieReg.io)),
GPIOCtrlRegs.out_xor -> Seq(RegField(c.width, xorReg))
swPinCtrl(pin).ds := dsReg(pin)
swPinCtrl(pin).ie := ieReg.io.q(pin)
- // Allow SW Override for invalid inputs.
- iof0Ctrl(pin) <> swPinCtrl(pin)
- when (io.port.iof_0(pin).o.valid) {
- iof0Ctrl(pin) <> io.port.iof_0(pin).o
+ val pre_xor = Wire(new GPIOPinCtrl())
+
+ if (c.includeIOF) {
+ // Allow SW Override for invalid inputs.
+ iof0Ctrl(pin) <> swPinCtrl(pin)
+ when (io.port.iof_0.get(pin).o.valid) {
+ iof0Ctrl(pin) <> io.port.iof_0.get(pin).o
+ }
+
+ iof1Ctrl(pin) <> swPinCtrl(pin)
+ when (io.port.iof_1.get(pin).o.valid) {
+ iof1Ctrl(pin) <> io.port.iof_1.get(pin).o
+ }
+
+ // Select IOF 0 vs. IOF 1.
+ iofCtrl(pin) <> Mux(iofSelReg(pin), iof1Ctrl(pin), iof0Ctrl(pin))
+
+ // Allow SW Override for things IOF doesn't control.
+ iofPlusSwPinCtrl(pin) <> swPinCtrl(pin)
+ iofPlusSwPinCtrl(pin) <> iofCtrl(pin)
+
+ // Final XOR & Pin Control
+ pre_xor := Mux(iofEnReg.io.q(pin), iofPlusSwPinCtrl(pin), swPinCtrl(pin))
+ } else {
+ pre_xor := swPinCtrl(pin)
}
- iof1Ctrl(pin) <> swPinCtrl(pin)
- when (io.port.iof_1(pin).o.valid) {
- iof1Ctrl(pin) <> io.port.iof_1(pin).o
- }
-
- // Select IOF 0 vs. IOF 1.
- iofCtrl(pin) <> Mux(iofSelReg(pin), iof1Ctrl(pin), iof0Ctrl(pin))
-
- // Allow SW Override for things IOF doesn't control.
- iofPlusSwPinCtrl(pin) <> swPinCtrl(pin)
- iofPlusSwPinCtrl(pin) <> iofCtrl(pin)
-
- // Final XOR & Pin Control
- val pre_xor: GPIOPinCtrl = Mux(iofEnReg.io.q(pin), iofPlusSwPinCtrl(pin), swPinCtrl(pin))
io.port.pins(pin).o := pre_xor
io.port.pins(pin).o.oval := pre_xor.oval ^ xorReg(pin)
(highIpReg(pin) & highIeReg(pin)) |
(lowIpReg(pin) & lowIeReg(pin))
- // Send Value to all consumers
- io.port.iof_0(pin).i.ival := inSyncReg(pin)
- io.port.iof_1(pin).i.ival := inSyncReg(pin)
+ if (c.includeIOF) {
+ // Send Value to all consumers
+ io.port.iof_0.get(pin).i.ival := inSyncReg(pin)
+ io.port.iof_1.get(pin).i.ival := inSyncReg(pin)
+ }
}
}
}
// Magic TL2 Incantation to create a TL2 Slave
-class TLGPIO(p: Parameters, c: GPIOConfig)
- extends TLRegisterRouter(c.address, interrupts = c.width, beatBytes = p(PeripheryBusConfig).beatBytes)(
- new TLRegBundle(Tuple2(p, c), _) with GPIOBundle)(
- new TLRegModule(Tuple2(p, c), _, _) with GPIOModule)
+class TLGPIO(w: Int, c: GPIOParams)(implicit p: Parameters)
+ extends TLRegisterRouter(c.address, "gpio", Seq("sifive,gpio0"), interrupts = c.width, beatBytes = w)(
+ new TLRegBundle(c, _) with HasGPIOBundleContents)(
+ new TLRegModule(c, _, _) with HasGPIOModuleContents)
projects / sifive-blocks.git / blobdiff