Refactor package hierarchy. (#25)

[sifive-blocks.git] / src / main / scala / devices / gpio / GPIOPeriphery.scala

diff --git a/src/main/scala/devices/gpio/GPIOPeriphery.scala b/src/main/scala/devices/gpio/GPIOPeriphery.scala
index 3c7a2ec41120cab68ac680c782d4199112223ef3..204f76782e13ad157c555163e0467e0aab941f1c 100644 (file)
--- a/src/main/scala/devices/gpio/GPIOPeriphery.scala
+++ b/src/main/scala/devices/gpio/GPIOPeriphery.scala
@@ -2,18 +2,15 @@
 package sifive.blocks.devices.gpio
 
 import Chisel._
-import config.Field
-import diplomacy.LazyModule
-import rocketchip.{
-  HasTopLevelNetworks,
-  HasTopLevelNetworksBundle,
-  HasTopLevelNetworksModule
-}
-import uncore.tilelink2.TLFragmenter
+import freechips.rocketchip.config.Field
+import freechips.rocketchip.diplomacy.{LazyModule,LazyMultiIOModuleImp}
+import freechips.rocketchip.chip.HasSystemNetworks
+import freechips.rocketchip.tilelink.TLFragmenter
+import freechips.rocketchip.util.HeterogeneousBag
 
 case object PeripheryGPIOKey extends Field[Seq[GPIOParams]]
 
-trait HasPeripheryGPIO extends HasTopLevelNetworks {
+trait HasPeripheryGPIO extends HasSystemNetworks {
   val gpioParams = p(PeripheryGPIOKey)
   val gpio = gpioParams map {params =>
     val gpio = LazyModule(new TLGPIO(peripheryBusBytes, params))
@@ -23,15 +20,15 @@ trait HasPeripheryGPIO extends HasTopLevelNetworks {
   }
 }
 
-trait HasPeripheryGPIOBundle extends HasTopLevelNetworksBundle {
-  val outer: HasPeripheryGPIO
-  val gpio = HeterogeneousBag(outer.gpioParams(map(new GPIOPortIO(_))))
+trait HasPeripheryGPIOBundle {
+  val gpio: HeterogeneousBag[GPIOPortIO]
 }
 
-trait HasPeripheryGPIOModule extends HasTopLevelNetworksModule {
+trait HasPeripheryGPIOModuleImp extends LazyMultiIOModuleImp with HasPeripheryGPIOBundle {
   val outer: HasPeripheryGPIO
-  val io: HasPeripheryGPIOBundle
-  (io.gpio zip outer.gpio) foreach { case (io, device) =>
-    io.gpio <> device.module.io.port
+  val gpio = IO(HeterogeneousBag(outer.gpioParams.map(new GPIOPortIO(_))))
+
+  (gpio zip outer.gpio) foreach { case (io, device) =>
+    io <> device.module.io.port
   }
 }