periphery: bus api update (#50)
[sifive-blocks.git] / src / main / scala / devices / gpio / GPIOPeriphery.scala
index b7a479cddbbfd23377090aae52b7a17c788c2c57..21fb6804b552f5be2167466b72cad3d29a08dc99 100644 (file)
@@ -2,20 +2,20 @@
 package sifive.blocks.devices.gpio
 
 import Chisel._
-import config.Field
-import diplomacy.{LazyModule,LazyMultiIOModuleImp}
-import rocketchip.HasSystemNetworks
-import uncore.tilelink2.TLFragmenter
-import util.HeterogeneousBag
+import freechips.rocketchip.config.Field
+import freechips.rocketchip.subsystem.BaseSubsystem
+import freechips.rocketchip.diplomacy.{LazyModule,LazyModuleImp}
+import freechips.rocketchip.util.HeterogeneousBag
 
 case object PeripheryGPIOKey extends Field[Seq[GPIOParams]]
 
-trait HasPeripheryGPIO extends HasSystemNetworks {
+trait HasPeripheryGPIO { this: BaseSubsystem =>
   val gpioParams = p(PeripheryGPIOKey)
-  val gpio = gpioParams map {params =>
-    val gpio = LazyModule(new TLGPIO(peripheryBusBytes, params))
-    gpio.node := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node)
-    intBus.intnode := gpio.intnode
+  val gpios = gpioParams.zipWithIndex.map { case(params, i) =>
+    val name = Some(s"gpio_$i")
+    val gpio = LazyModule(new TLGPIO(pbus.beatBytes, params)).suggestName(name)
+    pbus.toVariableWidthSlave(name) { gpio.node }
+    ibus.fromSync := gpio.intnode
     gpio
   }
 }
@@ -24,11 +24,11 @@ trait HasPeripheryGPIOBundle {
   val gpio: HeterogeneousBag[GPIOPortIO]
 }
 
-trait HasPeripheryGPIOModuleImp extends LazyMultiIOModuleImp with HasPeripheryGPIOBundle {
+trait HasPeripheryGPIOModuleImp extends LazyModuleImp with HasPeripheryGPIOBundle {
   val outer: HasPeripheryGPIO
   val gpio = IO(HeterogeneousBag(outer.gpioParams.map(new GPIOPortIO(_))))
 
-  (gpio zip outer.gpio) foreach { case (io, device) =>
+  (gpio zip outer.gpios) foreach { case (io, device) =>
     io <> device.module.io.port
   }
 }