src/main/scala/devices/gpio/GPIOPeriphery.scala

   1 // See LICENSE for license details.
   2 package sifive.blocks.devices.gpio
   3
   4 import Chisel._
   5 import freechips.rocketchip.config.Field
   6 import freechips.rocketchip.subsystem.BaseSubsystem
   7 import freechips.rocketchip.diplomacy.{LazyModule,LazyModuleImp}
   8 import freechips.rocketchip.util.HeterogeneousBag
   9
  10 case object PeripheryGPIOKey extends Field[Seq[GPIOParams]]
  11
  12 trait HasPeripheryGPIO { this: BaseSubsystem =>
  13   val gpioParams = p(PeripheryGPIOKey)
  14   val gpios = gpioParams.zipWithIndex.map { case(params, i) =>
  15     val name = Some(s"gpio_$i")
  16     val gpio = LazyModule(new TLGPIO(pbus.beatBytes, params)).suggestName(name)
  17     pbus.toVariableWidthSlave(name) { gpio.node }
  18     ibus.fromSync := gpio.intnode
  19     gpio
  20   }
  21 }
  22
  23 trait HasPeripheryGPIOBundle {
  24   val gpio: HeterogeneousBag[GPIOPortIO]
  25 }
  26
  27 trait HasPeripheryGPIOModuleImp extends LazyModuleImp with HasPeripheryGPIOBundle {
  28   val outer: HasPeripheryGPIO
  29   val gpio = IO(HeterogeneousBag(outer.gpioParams.map(new GPIOPortIO(_))))
  30
  31   (gpio zip outer.gpios) foreach { case (io, device) =>
  32     io <> device.module.io.port
  33   }
  34 }