spi: SPIParamsBase param needs to be public

[sifive-blocks.git] / src / main / scala / devices / gpio / GPIOPeriphery.scala

diff --git a/src/main/scala/devices/gpio/GPIOPeriphery.scala b/src/main/scala/devices/gpio/GPIOPeriphery.scala
index 38fd20ad8bdd2ee6bc7781fe1b8bc5afb4470ec4..21fb6804b552f5be2167466b72cad3d29a08dc99 100644 (file)
--- a/src/main/scala/devices/gpio/GPIOPeriphery.scala
+++ b/src/main/scala/devices/gpio/GPIOPeriphery.scala
@@ -2,37 +2,33 @@
 package sifive.blocks.devices.gpio
 
 import Chisel._
-import config.Field
-import diplomacy.LazyModule
-import rocketchip.{
-  HasTopLevelNetworks,
-  HasTopLevelNetworksBundle,
-  HasTopLevelNetworksModule
-}
-import uncore.tilelink2.TLFragmenter
-import util.HeterogeneousBag
+import freechips.rocketchip.config.Field
+import freechips.rocketchip.subsystem.BaseSubsystem
+import freechips.rocketchip.diplomacy.{LazyModule,LazyModuleImp}
+import freechips.rocketchip.util.HeterogeneousBag
 
 case object PeripheryGPIOKey extends Field[Seq[GPIOParams]]
 
-trait HasPeripheryGPIO extends HasTopLevelNetworks {
+trait HasPeripheryGPIO { this: BaseSubsystem =>
   val gpioParams = p(PeripheryGPIOKey)
-  val gpio = gpioParams map {params =>
-    val gpio = LazyModule(new TLGPIO(peripheryBusBytes, params))
-    gpio.node := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node)
-    intBus.intnode := gpio.intnode
+  val gpios = gpioParams.zipWithIndex.map { case(params, i) =>
+    val name = Some(s"gpio_$i")
+    val gpio = LazyModule(new TLGPIO(pbus.beatBytes, params)).suggestName(name)
+    pbus.toVariableWidthSlave(name) { gpio.node }
+    ibus.fromSync := gpio.intnode
     gpio
   }
 }
 
-trait HasPeripheryGPIOBundle extends HasTopLevelNetworksBundle {
-  val outer: HasPeripheryGPIO
-  val gpio = HeterogeneousBag(outer.gpioParams.map(new GPIOPortIO(_)))
+trait HasPeripheryGPIOBundle {
+  val gpio: HeterogeneousBag[GPIOPortIO]
 }
 
-trait HasPeripheryGPIOModule extends HasTopLevelNetworksModule {
+trait HasPeripheryGPIOModuleImp extends LazyModuleImp with HasPeripheryGPIOBundle {
   val outer: HasPeripheryGPIO
-  val io: HasPeripheryGPIOBundle
-  (io.gpio zip outer.gpio) foreach { case (io, device) =>
+  val gpio = IO(HeterogeneousBag(outer.gpioParams.map(new GPIOPortIO(_))))
+
+  (gpio zip outer.gpios) foreach { case (io, device) =>
     io <> device.module.io.port
   }
 }