import Chisel._
import freechips.rocketchip.config.Field
-import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus}
-import freechips.rocketchip.diplomacy.{LazyModule,LazyMultiIOModuleImp}
+import freechips.rocketchip.subsystem.BaseSubsystem
+import freechips.rocketchip.diplomacy.{LazyModule,LazyModuleImp}
import freechips.rocketchip.util.HeterogeneousBag
case object PeripheryGPIOKey extends Field[Seq[GPIOParams]]
-trait HasPeripheryGPIO extends HasPeripheryBus with HasInterruptBus {
+trait HasPeripheryGPIO { this: BaseSubsystem =>
val gpioParams = p(PeripheryGPIOKey)
- val gpios = gpioParams map { params =>
- val gpio = LazyModule(new TLGPIO(pbus.beatBytes, params))
- gpio.node := pbus.toVariableWidthSlaves
+ val gpios = gpioParams.zipWithIndex.map { case(params, i) =>
+ val name = Some(s"gpio_$i")
+ val gpio = LazyModule(new TLGPIO(pbus.beatBytes, params)).suggestName(name)
+ pbus.toVariableWidthSlave(name) { gpio.node }
ibus.fromSync := gpio.intnode
gpio
}
val gpio: HeterogeneousBag[GPIOPortIO]
}
-trait HasPeripheryGPIOModuleImp extends LazyMultiIOModuleImp with HasPeripheryGPIOBundle {
+trait HasPeripheryGPIOModuleImp extends LazyModuleImp with HasPeripheryGPIOBundle {
val outer: HasPeripheryGPIO
val gpio = IO(HeterogeneousBag(outer.gpioParams.map(new GPIOPortIO(_))))