import Chisel._
import chisel3.experimental.{withClockAndReset}
import freechips.rocketchip.config.Field
+import freechips.rocketchip.util.ShiftRegInit
import freechips.rocketchip.coreplex.{HasPeripheryBus, PeripheryBusParams, HasInterruptBus}
import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
import sifive.blocks.devices.pinctrl.{Pin}
-import sifive.blocks.util.ShiftRegisterInit
case object PeripheryUARTKey extends Field[Seq[UARTParams]]
withClockAndReset(clock, reset) {
txd.outputPin(uart.txd)
val rxd_t = rxd.inputPin()
- uart.rxd := ShiftRegisterInit(rxd_t, syncStages, Bool(true))
+ uart.rxd := ShiftRegInit(rxd_t, n = syncStages, init = Bool(true))
}
}
}